SNOSAW2Q September 2006 – November 2015 LM5100A , LM5100B , LM5100C , LM5101A , LM5101B , LM5101C
PRODUCTION DATA.
The bias supply voltage range for which the device is rated to operate is from 9 V to 14 V. The lower end of this range is governed by the internal under voltage-lockout (UVLO) protection feature on the VDD pin supply circuit blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the VDDR supply start threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is driven by the 18-V absolute maximum voltage rating of the VDD pin of the device (which is a stress rating). Keeping a 4-V margin to allow for transient voltage spikes, the maximum recommended voltage for the VDD pin is 14 V.
The UVLO protection feature also involves a hysteresis function. This means that when the VDD pin bias voltage has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification VDDH. Therefore, ensuring that, while operating at or near the 9-V range, the voltage ripple on the auxiliary power supply output is smaller than the hysteresis specification of the device is important to avoid triggering device shutdown.
During system shutdown, the device operation continues until the VDD pin voltage has dropped below the threshold (VDDR – VDDH), which must be accounted for while evaluating system shutdown timing design requirements. Likewise, at system start up, the device does not begin operation until the VDD pin voltage has exceeded above the VDDR threshold. The quiescent current consumed by the internal circuit blocks of the device is supplied through the VDD pin. Keep in mind that the charge for source current pulses delivered by the LO pin is also supplied through the same VDD pin. As a result, every time a current is sourced out of the LO pin a corresponding current pulse is delivered into the device through the VDD pin. Thus ensuring that a local bypass capacitor is provided between the VDD and GND pins and located as close as possible to the device for the purpose of decoupling is important. A low ESR, ceramic surface mount capacitor is necessary. TI recommends using two capacitors between VDD and GND: a 100-nF ceramic surface-mount capacitor that can be nudged very close to the pins of the device and another surface-mount capacitor in the range 0.22 µF to 10 µF added in parallel. In a similar manner, the current pulses delivered by the HO pin are sourced from the HB pin. Therefore, a 0.022-µF to 1-µF local decoupling capacitor is recommended between the HB and HS pins.