SNVS565I November 2008 – August 2015 LM5085 , LM5085-Q1
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
請參考 PDF 數據表獲取器件具體的封裝圖。
機械數據 (封裝 | 引腳)
- DGN|8
散熱焊盤機械數據 (封裝 | 引腳)
- DGN|8
訂購信息
5 Pin Configuration and Functions
8-Pins
HVSSOP Package
Top View
8-Pins
WSON Package
Top View
8-Pins
VSSOP Package
Top View
Pin Functions
| PIN | I/O | DESCRIPTION | APPLICATION INFORMATION | |
|---|---|---|---|---|
| NAME | NO. | |||
| ADJ | 1 | I | Current Limit Adjust | The current limit threshold is set by an external resistor from VIN to ADJ in conjunction with the external sense resistor or the PFET’s RDS(ON). |
| RT | 2 | I | On-Time Control and Shutdown | An external resistor from VIN to RT sets the buck switch on-time and switching frequency. Grounding this pin shuts down the controller. |
| FB | 3 | I | Voltage Feedback From the Regulated Output | Input to the regulation and over-voltage comparators. The regulation level is 1.25V. |
| GND | 4 | - | Circuit Ground | Ground reference for all internal circuitry |
| ISEN | 5 | I | Current Sense Input for Current limit Detection. | Connect to the PFET drain when using RDS(ON) current sense. Connect to the PFET source and the sense resistor when using a current sense resistor. |
| PGATE | 6 | O | Gate Driver Output | Connect to the gate of the external PFET. |
| VCC | 7 | O | Output of the gate driver bias regulator | Output of the negative voltage regulator (relative to VIN) that biases the PFET gate driver. A low ESR capacitor is required from VIN to VCC, located as close as possible to the pins. |
| VIN | 8 | I | Input Supply Voltage | The operating input range is from 4.5V to 75V. A low ESR bypass capacitor must be located as close as possible to the VIN and GND pins. |
| EP | - | Exposed Pad | Exposed pad on the underside of the package (HVSSOP and WSON only). This pad is to be soldered to the PC board ground plane to aid in heat dissipation. | |