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ZHCSJC9G September 2006 – Jaunuary 2020 LM5069

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

DGS|10
- MPDS035C

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6.5 Electrical Characteristics

Minimum and maximum limits are specified through test, design, or statistical correlation at T_J= –40°C to 125°C. Typical values represent the most likely parametric norm at T_J = 25°C and are provided for reference purposes only. VIN = 48 V (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT (VIN PIN)
I_IN-EN	Input current, enabled	UVLO > 2.5 V and OVLO < 2.5 V		1.3	1.6	mA
I_IN-DIS	Input current, disabled	UVLO < 2.5 V or OVLO > 2.5 V		480	650	µA
POR_IT	Power-On reset threshold at VIN to trigger insertion timer	VIN increasing		7.6	8	V
POR_EN	Power-On reset threshold at VIN to enable all functions	VIN increasing		8.4	9	V
POR_EN-HYS	POR_EN hysteresis	VIN decreasing		90		mV
OUT PIN
I_OUT-EN	OUT bias current, enabled	OUT = VIN, Normal operation		11		µA
I_OUT-DIS	OUT bias current, disabled⁽¹⁾	Disabled, OUT = 0 V, SENSE = VIN		50		µA
UVLO, OVLO PINS
UVLO_TH	UVLO threshold		2.45	2.5	2.55	V
UVLO_HYS	UVLO hysteresis current	UVLO = 1 V	12	21	30	µA
UVLO_DEL	UVLO delay	Delay to GATE high		55		µs
UVLO_DEL	UVLO delay	Delay to GATE low		11		µs
UVLO_BIAS	UVLO bias current	UVLO = 48 V			1	µA
OVLO_TH	OVLO threshold		2.4	2.5	2.6	V
OVLO_HYS	OVLO hysteresis current	OVLO = 2.6 V	12	21	30	µA
OVLO_DEL	OVLO delay	Delay to GATE high		55		µs
OVLO_DEL	OVLO delay	Delay to GATE low		11		µs
OVLO_BIAS	OVLO bias current	OVLO = 2.4 V			1	µA
POWER LIMIT (PWR PIN)
PWR_LIM-1	Power limit sense voltage (VIN-SENSE)	SENSE-OUT = 48 V, R_PWR = 150 kΩ	19	25	31	mV
PWR_LIM-2	Power limit sense voltage (VIN-SENSE)	SENSE-OUT = 24 V, R_PWR = 75 kΩ		25		mV
I_PWR	PWR pin current	V_PWR = 2.5 V		20		µA
GATE CONTROL (GATE PIN)
I_GATE	Source current	Normal operation, GATE-OUT = 5 V	10	16	22	µA
	Sink current	UVLO < 2.5 V	1.75	2	2.6	mA
	Sink current	VIN to SENSE = 150 mV or VIN < POR_IT, V_GATE = 5 V	45	110	175	mA
V_GATE	Gate output voltage in normal operation	GATE-OUT voltage	11.4	12	12.6	V
CURRENT LIMIT
V_CL	Threshold voltage	VIN-SENSE voltage	48.5	55	61.5	mV
t_CL	Response time	VIN-SENSE stepped from 0 mV to 80 mV		45		µs
I_SENSE	SENSE input current	Enabled, SENSE = OUT		23		µA
I_SENSE	SENSE input current	Disabled, OUT = 0 V		60		µA
CIRCUIT BREAKER
V_CB	Threshold voltage	VIN to SENSE	80	105	130	mV
t_CB	Response time	VIN to SENSE stepped from 0 mV to 150 mV, time to GATE low, no load		0.44	1.2	µs
TIMER (TIMER PIN)
V_TMRH	Upper threshold		3.76	4	4.16	V
V_TMRL	Lower threshold	Restart cycles (LM5069-2)	1.187	1.25	1.313	V
		End of 8th cycle (LM5069-2)		0.3		V
		Re-enable Threshold (LM5069-1)		0.3		V
I_TIMER	Insertion time current		3	5.5	8	µA
	Sink current, end of insertion time	TIMER pin = 2 V	1	1.5	2	mA
	Fault detection current		51	85	120	µA
	Fault sink current		1.25	2.5	3.75	µA
DC_FAULT	Fault restart duty cycle	LM5069-2 only		0.5%
t_FAULT	Fault to GATE low delay	TIMER pin reaches 4 V		12		µs
POWER GOOD (PGD PIN)
PGD_TH	Threshold measured at SENSE-OUT	Decreasing	0.67	1.25	1.85	V
PGD_TH	Threshold measured at SENSE-OUT	Increasing, relative to decreasing threshold	0.95	1.25	1.55	V
PGD_VOL	Output low voltage	I_SINK = 2 mA		60	150	mV
PGD_IOH	Off leakage current	V_PGD= 80 V			5	µA

(1) OUT bias current (disabled) due to leakage current through an internal 1-MΩ resistance from SENSE to VOUT.