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SNVS293F December 2004 – August 2016 LM5025A

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

PW|16
- MPDS361B
NHQ|16
- MPDS425

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

	MIN	MAX	UNIT
V_IN to GND	–0.3	105	V
V_CC to GND	–0.3	16	V
CS1, CS2 to GND	–0.3	1	V
All other inputs to GND	–0.3	7	V
Junction temperature, T_J		150	°C
Storage temperature, T_stg	–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM)⁽¹⁾	±2000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
V_IN voltage	13	90	V
External voltage applied to V_CC	8	15	V
Operating junction temperature	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LM5025A		UNIT
		PW (TSSOP)	NHQ (WSON)
		16 PINS	16 PINS
R_θJA	Junction-to-ambient thermal resistance	98.7	30	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	27.8	25.9	°C/W
R_θJB	Junction-to-board thermal resistance	44.3	9.3	°C/W
ψ_JT	Junction-to-top characterization parameter	1.2	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	43.6	9.5	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	—	2.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Typical limits are for T_J = 25°C, and minimum and maximum limits apply over the operating junction temperature range (–40°C to 125°C). V_IN = 48 V, V_CC = 10 V, RT = 31.3 kΩ, R_SET = 27.4 kΩ) unless otherwise stated ⁽¹⁾

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
START-UP REGULATOR
V_CC Reg	V_CC regulation	No load	T_J = 25°C		7.6		V
V_CC Reg	V_CC regulation	No load	T_J = T_low to T_high	7.3		7.9	V
	V_CC current limit	See ⁽²⁾	T_J = 25°C		25		mA
	V_CC current limit	See ⁽²⁾	T_J = T_low to T_high	20			mA
I-V_IN	Start-up regulator leakage (external Vcc Supply)	V_IN = 100 V	T_J = 25°C		165		µA
I-V_IN	Start-up regulator leakage (external Vcc Supply)	V_IN = 100 V	T_J = T_low to T_high			500	µA
V_CC SUPPLY
	V_CC undervoltage lockout voltage (positive going V_cc)	T_J = 25°C			V_CC Reg - 120 mV		V
	V_CC undervoltage lockout voltage (positive going V_cc)	T_J = T_low to T_high		V_CC Reg - 220 mV			V
	V_CC undervoltage hysteresis	T_J = 25°C			1.5		V
	V_CC undervoltage hysteresis	T_J = T_low to T_high		1		2	V
	V_CC supply current (I_CC)	C_gate = 0	T_J = T_low to T_high			4.2	mA
REFERENCE SUPPLY
V_REF	Ref voltage	I_REF = 0 mA	T_J = 25°C		5		V
	Ref voltage	I_REF = 0 mA	T_J = T_low to T_high	4.85		5.15	V
	Ref voltage regulation	I_REF = 0 to 10mA	T_J = 25°C		25		mV
	Ref voltage regulation	I_REF = 0 to 10mA	T_J = T_low to T_high			50	mV
	Ref current limit	T_J = 25°C			20		mA
	Ref current limit	T_J = T_low to T_high		10			mA
CURRENT LIMIT
CS1 Prop	CS1 delay to output	CS1 Step from 0 to 0.6 V, Time to onset of OUT Transition (90%), C_gate = 0			40		ns
CS2 Prop	CS2 delay to output	CS2 Step from 0 to 0.6 V, Time to onset of OUT Transition (90%), C_gate = 0			50		ns
	Cycle by cycle threshold voltage (CS1)	T_J = 25°C			0.5		V
	Cycle by cycle threshold voltage (CS1)	over full operating junction temperature		0.45		0.55	V
	Cycle skip threshold voltage (CS2)	Resets SS capacitor; auto restart	T_J = 25°C		0.5		V
	Cycle skip threshold voltage (CS2)	Resets SS capacitor; auto restart	T_J = T_low to T_high	0.45		0.55	V
	Leading edge blanking time (CS1)				50		ns
	CS1 sink impedance (clocked)	CS1 = 0.4 V	T_J = 25°C		30		Ω
	CS1 sink impedance (clocked)	CS1 = 0.4 V	T_J = T_low to T_high			50	Ω
	CS1 sink impedance (post fault discharge)	CS1 = 0.6 V	T_J = 25°C		15		Ω
	CS1 sink impedance (post fault discharge)	CS1 = 0.6 V	T_J = T_low to T_high			30	Ω
	CS2 sink impedance (post fault discharge)	CS2 = 0.6 V	T_J = 25°C		55		Ω
	CS2 sink impedance (post fault discharge)	CS2 = 0.6 V	T_J = T_low to T_high			95	Ω
	CS1 and CS2 leakage current	CS = CS Threshold – 100 mV	T_J = T_low to T_high			1	µA
SOFT-START
	Soft-start current source normal	T_J = 25°C			22		µA
	Soft-start current source normal	over full operating junction temperature		17		27	µA
	Soft-start current source following a CS2 event	T_J = 25°C			1		µA
	Soft-start current source following a CS2 event	over full operating junction temperature		0.5		1.5	µA
OSCILLATOR
	Frequency1	T_A = 25°C,		180	200	220	kHz
	Frequency1	T_J = T_low to T_high		175		225	kHz
	Frequency2	RT = 10.4 kΩ	T_A = 25°C,		580		kHz
	Frequency2	RT = 10.4 kΩ	T_J = T_low to T_high	510		650	kHz
	Sync threshold				2		V
	Min sync pulse width	T_J = T_low to T_high				100	ns
	Sync frequency range	T_J = T_low to T_high		160			kHz
PWM COMPARATOR
	Delay to output	COMP step 5 V to 0 V, Time to onset of OUT_A transition low			40		ns
	Duty cycle range	T_J = T_low to T_high		0%		80%
	COMP to PWM offset	T_A = 25°C,			1		V
	COMP to PWM offset	T_J = T_low to T_high		0.7		1.3	V
	COMP open-circuit voltage	T_J = T_low to T_high		4.3		5.9	V
	COMP short-circuit current	COMP = 0 V	T_A = 25°C,		1		mA
	COMP short-circuit current	COMP = 0 V	T_J = T_low to T_high	0.6		1.4	mA
VOLT × SECOND CLAMP
	Ramp clamp level	Delta RAMP measured from onset of OUT_A to Ramp peak, COMP = 5 V	T_A = 25°C,		2.5		V
	Ramp clamp level		T_J = T_low to T_high	2.4		2.6	V
UVLO SHUTDOWN
	Undervoltage shutdown threshold	T_A = 25°C,			2.5		V
	Undervoltage shutdown threshold	T_J = T_low to T_high		2.44		2.56	V
	Undervoltage shutdown hysteresis	T_A = 25°C,			20		µA
	Undervoltage shutdown hysteresis	T_J = T_low to T_high		16		24	µA
OUTPUT SECTION
	OUT_A high saturation	MOS device at Iout = –10 mA	T_A = 25°C,		5		Ω
	OUT_A high saturation	MOS device at Iout = –10 mA	T_J = T_low to T_high			10	Ω
	OUTPUT_A peak current sink	Bipolar Device at Vcc/2			3		A
	OUT_A low saturation	MOS device at Iout = 10 mA	T_A = 25°C,		6		Ω
	OUT_A low saturation	MOS device at Iout = 10 mA	T_J = T_low to T_high			9	Ω
	OUTPUT_A rise time	C_gate = 2.2 nF			20		ns
	OUTPUT_A fall time	C_gate = 2.2 nF			15		ns
	OUT_B high saturation	MOS device at Iout = –10 mA	T_A = 25°C,		10		Ω
	OUT_B high saturation	MOS device at Iout = –10 mA	T_J = T_low to T_high			20	Ω
	OUTPUT_B peak current sink	Bipolar device at Vcc/2			1		A
	OUT_B low saturation	MOS device at Iout = 10 mA	T_A = 25°C,		12		Ω
	OUT_B low saturation	MOS device at Iout = 10 mA	T_J = T_low to T_high			18	Ω
	OUTPUT_B rise time	C_gate = 1 nF			20		ns
	OUTPUT_B fall time	C_gate = 1 nF			15		ns
OUTPUT TIMING CONTROL
	Overlap time	R_SET = 38 kΩ connected to GND, 50% to 50% transitions	T_A = 25°C,		105		ns
	Overlap time	R_SET = 38 kΩ connected to GND, 50% to 50% transitions	T_J = T_low to T_high	75		135	ns
	Dead time	R_SET = 29.5 kΩ connected to REF, 50% to 50% transitions	T_A = 25°C,		105		ns
	Dead time	R_SET = 29.5 kΩ connected to REF, 50% to 50% transitions	T_J = T_low to T_high	75		135	ns
THERMAL SHUTDOWN
T_SD	Thermal shutdown threshold				165		°C
	Thermal shutdown hysteresis				25		°C

(1) All electrical characteristics having room temperature limits are tested during production with T_A = T_J = 25°C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

(2) Device thermal limitations may limit usable range.