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ZHCSHC6I January 2007 – December 2017 LM5022

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

DGS|10
- MPDS035C

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6.5 Electrical Characteristics

Typical limits apply for T_J=25°C and are provided for reference purposes only; minimum and maximum limits apply over the junction temperature (T_J) range of –40°C to 125°C. V_IN = 24 V and R_T = 27.4 kΩ (unless otherwise noted).⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SYSTEM PARAMETERS
V_FB	FB pin voltage		1.225	1.25	1.275	V
STARTUP REGULATOR
VCC	VCC regulation⁽²⁾	10 V ≤ V_IN ≤ 60 V, I_CC = 1 mA	6.6	7	7.4	V
VCC	VCC regulation⁽²⁾	6 V ≤ V_IN< 10V, VCC Pin Open Circuit	5			V
I_CC	Supply current	OUT Pin Capacitance = 0, VCC = 10 V		3.5	4	mA
I_CC-LIM	VCC current limit	VCC = 0 V⁽²⁾⁽³⁾	15	35		mA
V_IN - VCC	Dropout voltage across bypass switch	I_CC = 0 mA, ƒ_SW< 200 kHz, 6 V ≤ V_IN ≤ 8.5 V		200		mV
V_BYP-HI	Bypass switch turnoff threshold	V_IN increasing		8.7		V
V_BYP-HYS	Bypass switch threshold hysteresis	V_IN Decreasing		260		mV
Z_VCC	VCC pin output impedance 0 mA ≤ ICC ≤ 5 mA	V_IN = 6 V		58		Ω
		V_IN = 8 V		53
		V_IN = 24 V		1.6
VCC_-HI	VCC pin UVLO rising threshold			5		V
VCC_-HYS	VCC pin UVLO falling hysteresis			300		mV
I_VIN	Startup regulator leakage	V_IN = 60 V		150	500	µA
I_IN-SD	Shutdown current	V_UVLO = 0 V, VCC = Open Circuit		350	450	µA
ERROR AMPLIFIER
GBW	Gain bandwidth			4		MHz
A_DC	DC gain			75		dB
I_COMP	COMP pin current sink capability	V_FB = 1.5 V, V_COMP = 1 V	5	17		mA
UVLO
V_SD	Shutdown threshold		1.22	1.25	1.28	V
I_SD-HYS	Shutdown hysteresis current source		16	20	24	µA
CURRENT LIMIT
t_LIM-DLY	Delay from ILIM to output	CS steps from 0 V to 0.6 V, OUT transitions to 90% of VCC		30		ns
V_CS	Current limit threshold voltage		0.45	0.5	0.55	V
t_BLK	Leading edge blanking time			65		ns
R_CS	CS pin sink impedance	Blanking active		40	75	Ω
SOFT START
I_SS	Soft-start current source		7	10	13	µA
V_SS-OFF	Soft start to COMP offset		0.35	0.55	0.75	V
OSCILLATOR
f_SW	RT to GND = 84.5 kΩ		170⁽⁴⁾	200	230	kHz
	RT to GND = 27.4 kΩ	See⁽⁴⁾	525	600	675	kHz
	RT to GND = 16.2 kΩ	See⁽⁴⁾	865	990	1115	kHz
V_SYNC-HI	Synchronization rising threshold				3.8	V
PWM COMPARATOR
t_COMP-DLY	Delay from COMP to OUT transition	V_COMP = 2 V, CS stepped from 0 V to 0.4 V		25		ns
D_MIN	Minimum duty cycle	V_COMP = 0 V			0%
D_MAX	Maximum duty cycle		90%	95%
A_PWM	COMP to PWM comparator gain			0.33		V/V
V_COMP-OC	COMP pin open circuit voltage	V_FB = 0 V	4.3	5.2	6.1	V
I_COMP-SC	COMP pin short circuit current	V_COMP = 0 V, V_FB = 1.5 V	0.6	1.1	1.5	mA
SLOPE COMPENSATION
V_SLOPE	Slope compensation amplitude		83	110	137	mV
MOSFET DRIVER
V_SAT-HI	Output high saturation voltage (VCC – VOUT)	I_OUT = 50 mA		0.25	0.75	V
V_SAT-LO	Output low saturation voltage (VOUT)	I_OUT = 100 mA		0.25	0.75	V
t_RISE	OUT pin rise time	OUT Pin load = 1 nF		18		ns
t_FALL	OUT pin fall time	OUT Pin load = 1 nF		15		ns
THERMAL CHARACTERISTICS
T_SD	Thermal shutdown threshold			165		°C
T_SD-HYS	Thermal shutdown hysteresis			25		°C

(1) All Minimum and Maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. The junction temperature (T_J in °C) is calculated from the ambient temperature (T_A in °C) and power dissipation (P_D in Watts) as follows: T_J = T_A + (P_D × R_θJA) where R_θJA (in °C/W) is the package thermal impedance provided in Thermal Information.

(2) VCC provides bias for the internal gate drive and control circuits.

(3) Device thermal limitations may limit usable range.

(4) Specification applies to the oscillator frequency.