7.3.5 VCC, UVLO, and BIAS

The LM46000-Q1 integrates an internal LDO to generate V_CC for control circuitry and MOSFET drivers. The nominal voltage for V_CC is 3.3 V. The VCC pin is the output of the LDO and must be properly bypassed. A high-quality ceramic capacitor with 2.2-µF to 10-µF capacitance and 6.3 V or higher rated voltage must be placed as close as possible to VCC and grounded to the exposed PAD and ground pins. The VCC output pin must not be loaded, left floating, connected to any external supply, or shorted to ground during operation. Shorting VCC to ground during operation may cause damage to the LM46000-Q1.

Undervoltage lockout (UVLO) prevents the LM46000-Q1 from operating until the V_CC voltage exceeds 3.14 V (typical). The V_CC UVLO threshold has 567 mV of hysteresis (typically) to prevent undesired shutting down due to temporary V_IN droops.

The internal LDO has two inputs: primary from VIN and secondary from BIAS input. The BIAS input powers the LDO when V_BIAS is higher than the changeover threshold. Power loss of an LDO is calculated by I_LDO × (V_IN-LDO – V_OUT-LDO). The higher the difference between the input and output voltages of the LDO, the more power loss occur to supply the same output current. The BIAS input is designed to reduce the difference of the input and output voltages of the LDO to reduce power loss and improve LM46000-Q1 efficiency, especially at light load. TI recommends tying the BIAS pin to V_OUT when V_OUT ≥ 3.3 V. Ground the BIAS pin in applications with V_OUT less than 3.3 V. BIAS input can also come from an external voltage source, if available, to reduce power loss. When used, TI recommends a 1-µF to 10-µF, high-quality ceramic capacitorto bypass the BIAS pin to ground.