ZHCSIQ5A September 2018 – August 2021 LM34936
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed Frequency Valley/Peak Current Mode Control with Slope Compensation
- 7.3.2 VCC Regulator and Optional BIAS Input
- 7.3.3 Enable/UVLO
- 7.3.4 Soft-Start
- 7.3.5 Overcurrent Protection
- 7.3.6 Average Input/Output Current Limiting
- 7.3.7 Operation Above 28-V Input
- 7.3.8 CCM Operation
- 7.3.9 Frequency and Synchronization (RT/SYNC)
- 7.3.10 Frequency Dithering
- 7.3.11 Output Overvoltage Protection (OVP)
- 7.3.12 Power Good (PGOOD)
- 7.3.13 Gm Error Amplifier
- 7.3.14 Integrated Gate Drivers
- 7.3.15 Thermal Shutdown
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Custom Design with WEBENCH Tools
- 8.2.2.2 Frequency
- 8.2.2.3 VOUT
- 8.2.2.4 Inductor Selection
- 8.2.2.5 Output Capacitor
- 8.2.2.6 Input Capacitor
- 8.2.2.7 Sense Resistor (RSENSE)
- 8.2.2.8 Slope Compensation
- 8.2.2.9 UVLO
- 8.2.2.10 Soft-Start Capacitor
- 8.2.2.11 Dither Capacitor
- 8.2.2.12 MOSFETs QH1 and QL1
- 8.2.2.13 MOSFETs QH2 and QL2
- 8.2.2.14 Frequency Compensation
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
5 Pin Configuration and Functions
Figure 5-1 QFN-28RHF PackageTop ViewTable 5-1 Pin Functions
| PIN | DESCRIPTION | ||
|---|---|---|---|
| NO. | NAME | ||
| 1 | MODE | 1.38 V < MODE < 2.22 V : CCM, Hiccup Enabled (Set RMODE resistor to AGND = 93.1 k?). 2.6 V < MODE < VCC: CCM, Hiccup Disabled (Set RMODE resistor to AGND = 200 k? or connect to VCC) | |
| 2 | DITH | A capacitor connected between the DITH pin and AGND is charged and discharged with a current source. As the voltage on the DITH pin ramps up and down the oscillator frequency is modulated by 10% of the nominal frequency set by the RT resistor. Grounding the DITH pin will disable the dithering feature. In the external Sync mode, the DITH pin voltage is ignored. | |
| 3 | RT/SYNC | Switching frequency programming pin. An external resistor is connected to the RT/SYNC pin and AGND to set the switching frequency. This pin can also be used to synchronize the PWM controller to an external clock. | |
| 4 | SLOPE | A capacitor connected between the SLOPE pin and AGND provides the slope compensation ramp for stable current mode operation in both buck and boost mode. | |
| 5 | SS | Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start time. | |
| 6 | COMP | Output of the error amplifier. An external RC network connected between COMP and AGND compensates the regulator feedback loop. | |
| 7 | AGND | Analog ground of the IC. | |
| 8 | FB | Feedback pin for output voltage regulation. Connect a resistor divider network from the output of the converter to the FB pin. | |
| 9 | VOSNS | VOUT sense input. Connect to the power stage output rail. | |
| 10 11 |
ISNS(–) ISNS(+) |
Input or Output Current Sense Amplifier inputs. An optional current sense resistor connected between ISNS(+) and ISNS(–) can be located either on the input side or on the output side of the converter. If the sensed voltage across the ISNS(+) and ISNS(-) pins reaches 50 mV, a slow Constant Current (CC) control loop becomes active and starts discharging the soft-start capacitor to regulate the drop across ISNS(+) and ISNS(-) to 50 mV. Short ISNS(+) and ISNS(-) together to disable this feature. | |
| 12 | CSG | The negative or ground input to the PWM current sense amplifier. Connect directly to the low-side (ground) of the current sense resistor. | |
| 13 | CS | The positive input to the PWM current sense amplifier. | |
| 14 | PGOOD | Power Good open drain output. PGOOD is pulled low when FB is outside a -9%/+10% regulation window around the 0.8-V VREF. | |
| 15 25 |
SW2 SW1 |
The boost and the buck side switching nodes respectively. | |
| 16 24 |
HDRV2 HDRV1 |
Output of the high-side gate drivers. Connect directly to the gates of the high-side MOSFETs. | |
| 17 23 |
BOOT2 BOOT1 |
An external capacitor is required between the BOOT1, BOOT2 pins and the SW1, SW2 pins respectively to provide bias to the high-side MOSFET gate drivers. | |
| 18 22 |
LDRV2 LDRV1 |
Output of the low-side gate drivers. Connect directly to the gates of the low-side MOSFETs. | |
| 19 | PGND | Power ground of the IC. The high current ground connection to the low-side gate drivers. | |
| 20 | VCC | Output of the VCC bias regulator. Connect capacitor to ground. | |
| 21 | BIAS | Optional input to the VCC bias regulator. Powering VCC from an external supply instead of VIN can reduce power loss at high VIN. For VBIAS > 8 V, the VCC regulator draws power from the BIAS pin. | |
| 26 | EN/UVLO | Enable pin. For EN/UVLO < 0.4 V, the LM34936 is in a low current shutdown mode. For EN/UVLO > 1.22 V, the PWM function is enabled, provided VCC exceeds the VCC UV threshold. | |
| 27 | VIN | The input supply pin to the IC. Connect VIN to a supply voltage between 4.2 V and 30 V. | |
| 28 | VISNS | VIN sense input. Connect to power stage input rail. | |
| - | PowerPAD? | The PowerPAD should be soldered to the analog ground. If possible, use thermal vias to connect to a PCB ground plane for improved power dissipation. | |