ZHCSD58G June 2012 – November 2017 LM34925
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Control Overview
- 7.3.2 VCC Regulator
- 7.3.3 Regulation Comparator
- 7.3.4 Overvoltage Comparator
- 7.3.5 On-Time Generator
- 7.3.6 Current Limit
- 7.3.7 N-Channel Buck Switch and Driver
- 7.3.8 Synchronous Rectifier
- 7.3.9 Undervoltage Detector
- 7.3.10 Thermal Protection
- 7.3.11 Ripple Configuration
- 7.3.12 Soft Start
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1
Application Circuit: 20-V to 95-V Input and 10-V, 100-mA Output Isolated Fly-Buck Converter
- 8.2.1.1 Design Requirements
- 8.2.1.2
Detailed Design Procedure
- 8.2.1.2.1 Transformer Turns Ratio
- 8.2.1.2.2 Total IOUT
- 8.2.1.2.3 RFB1, RFB2
- 8.2.1.2.4 Frequency Selection
- 8.2.1.2.5 Transformer Selection
- 8.2.1.2.6 Primary Output Capacitor
- 8.2.1.2.7 Secondary Output Capacitor
- 8.2.1.2.8 Type III Feedback Ripple Circuit
- 8.2.1.2.9 Secondary Diode
- 8.2.1.2.10 VCC and Bootstrap Capacitor
- 8.2.1.2.11 Input Capacitor
- 8.2.1.2.12 UVLO Resistors
- 8.2.1.2.13 VCC Diode
- 8.2.2 Application Curves
- 8.2.1
Application Circuit: 20-V to 95-V Input and 10-V, 100-mA Output Isolated Fly-Buck Converter
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
- DDA|8
訂購信息
8.2.1.2.11 Input Capacitor
The input capacitor is typically a combination of a smaller bypass capacitor located near the regulator IC and a larger bulk capacitor. The total input capacitance should be large enough to limit the input voltage ripple to a desired amplitude. For input ripple voltage ΔVIN, CIN can be calculated using Equation 18.
Choosing a ΔVIN of 0.5 V gives a minimum CIN of 0.067 μF. A standard value of 0.1 μF is selected for CBYP in this design. A bulk capacitor of higher value reduces voltage spikes due to parasitic inductance between the power source to the converter. A standard value of 1 μF is selected for CIN in this design. The voltage ratings of the two input capacitors should be greater than the maximum input voltage under all conditions.