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ZHCSH33Z September 1997 – April 2025 LM317

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

KCS|3
- MPSF053A
KTT|3
- MPSF006E
DCY|4
- MPDS094A

散熱焊盤機械數據 (封裝 | 引腳)

KTT|3
- PPTD068B
DCY|4
- QFND222B

訂購信息

6.6 Electrical Characteristics

some specifications apply over the full operating temperature range as noted; unless otherwise specified, T_J = 25°C, V_IN ? V_OUT = 5V, and I_OUT = 10mA⁽¹⁾

PARAMETER	TEST CONDITIONS⁽¹⁾			MIN	TYP	MAX	UNIT
Reference voltage	T_J = 25°C				1.25		V
Reference voltage	3V ≤ (V_IN ? V_OUT) ≤ 40V, 10mA ≤ I_OUT ≤ 1500mA, P_D ≤ 20W			1.2	1.25	1.3	V
Line regulation⁽²⁾	3V ≤ (V_IN ? V_OUT) ≤ 40V⁽⁴⁾		T_J = 25°C		0.01	0.04	%/V
Line regulation⁽²⁾	3V ≤ (V_IN ? V_OUT) ≤ 40V⁽⁴⁾		(over full operating temperature range)		0.02	0.07	%/V
Load regulation	Legacy chip	I_O = 10mA to 1500mA, C_ADJ = 10μF⁽³⁾, T_J = 25°C	V_O ≤ 5V			25	mV
		I_O = 10mA to 1500mA, C_ADJ = 10μF⁽³⁾, T_J = 25°C	V_O ≥ 5V		0.1	0.5	%V_O
		I_O = 10mA to 1500mA, T_J = 0°C to 125°C	V_O ≤ 5V		20	70	mV
		I_O = 10mA to 1500mA, T_J = 0°C to 125°C	V_O ≥ 5V		0.3	1.5	%V_O
	New chip	10mA ≤ I_OUT ≤ I_MAX⁽⁵⁾	T_J = 25°C		0.1	0.5
	New chip	10mA ≤ I_OUT ≤ I_MAX⁽⁵⁾	(over full operating temperature range)		0.3	1.5
Thermal regulation	20ms pulse				0.04	0.07	%/W
Adjustment pin current	Over full operating temperature range				50	100	μA
Adjustment pin current change	10mA ≤ I_OUT ≤ I_MAX⁽⁴⁾ 3V ≤ (V_IN ? V_OUT) ≤ 40V		Over full operating temperature range		0.2	5	μA
Temperature stability	Legacy chip	T_MIN ≤ T_J ≤ T_MAX	Over full operating temperature range		0.7		%V_O
Temperature stability	New chip	T_MIN ≤ T_J ≤ T_MAX	Over full operating temperature range		1%		%V_O
Minimum load current	(V_IN ? V_OUT) = 40V		Over full operating temperature range		3.5	10	mA
Current limit	(V_IN ? V_OUT) ≤ 15V?		P_D < P_MAX⁽³⁾	1.5	2.2		A
Current limit	(V_IN ? V_OUT) = 40V		P_D < P_MAX⁽³⁾, T_J = 25°C	0.15	0.4		A
RMS output noise, % of V_OUT	10Hz ≤ f ≤ 10kHz				0.003		%
Ripple rejection ratio	Legacy chip	V_OUT = 10V, f = 120Hz, C_ADJ = 0μF⁽⁴⁾			57		dB
	Legacy chip	V_OUT = 10V, f = 120Hz, C_ADJ = 10μF⁽⁴⁾		62	64
	New chip	V_OUT = 10V, f = 120Hz, C_ADJ = 0μF (over full operating temperature range)			65
	New chip	V_OUT = 10V, f = 120Hz, C_ADJ = 10μF (over full operating temperature range)		66	80
Long-term stability	T_J = 25°C				0.3	1	%/1k hr

(1) For the legacy chip (unless otherwise noted), the following test conditions apply: |V_I – V_O| = 5V, I_OMAX = 1.5A, and T_J = 0°C to 125°C. Pulse testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible.

(2) For the legacy chip, line regulation is expressed as the percentage change in output voltage per 1V change at the input.

(3) For the legacy chip, maximum power dissipation is a function of T_J(max), R_θJA, and T_A. The maximum allowable power dissipation at any allowable ambient temperature is P_D = (T_J(max) – T_A) / R_θJA. Operating at the absolute maximum T_J of 150°C potentially affects reliability.

(4) For the legacy chip, C_ADJ is connected between the ADJUST pin and GND.

(5) For the new chip, regulation is measured at a constant junction temperature, using pulse testing with a low duty cycle. Changes in output voltage resulting from heating effects are covered under the specifications for thermal regulation.