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SNOSC66D MARCH 2012 – September 2016 LM3017

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

NKL|10
- MPQF311

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

	MIN	MAX	UNIT
VIN to PGND, AGND	–0.3	20	V
FB, COMP, VCC,DR to PGND, AGND	–0.2	6	V
EN/MODE	–0.2	5.5	V
VG	–0.3	VIN + 6	V
ISEN to PGND, AGND	VIN – 0.3	VIN	V
Peak low side driver output current		1	A
Power dissipation	Internally limited
Junction temperature, T_J		150	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Supply voltage	5.4	18	V
T_J	Junction temperature	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LM3017	UNIT
		NKL (WQFN)
		10 PINS
R_θJA	Junction-to-ambient thermal resistance	79.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	29.8	°C/W
R_θJB	Junction-to-board thermal resistance	21.4	°C/W
ψ_JT	Junction-to-top characterization parameter	0.6	°C/W
ψ_JB	Junction-to-board characterization parameter	20.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	—	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Minimum and maximum limits are specified through test, design, or statistical correlation, and apply over the junction temperature range at T_J = –40°C to 125°C. Typical values are provided for reference purposes only, and represent the most likely parametric norm at T_J = 25°C. V_IN = 12 V (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN⁽¹⁾	TYP⁽²⁾	MAX⁽¹⁾	UNIT
V_FB	Feedback voltage	Vcomp = 1.4 V	1.256	1.27	1.282	V
ΔV_LINE	Feedback voltage line regulation	5 V ≤ V_IN ≤ 18 V		0.33%
V_UVLO	Input undervoltage lockout voltage	Rising	4.6	4.82	4.9	V
V_UVLO	Input undervoltage lockout hysteresis	Falling, below V_UVLO		280		mV
F_SW	Nominal switching frequency	EN/MODE = 1.6 V	550	600	635	kHz
R_DS(ON)	Low-side NMOS driver resistance, top driver FET	V_IN = 5 V, I_DR = 0.2 A		3.4		Ω
R_DS(ON)	Low-side NMOS driver resistance, bottom driver FET	V_IN = 5 V, I_DR = 0.2 A		1		Ω
VCC	Driver voltage supply	V_IN < 6 V		V_IN		V
VCC	Driver voltage supply	V_IN ≥ 6 V		5.6
D_max	Maximum duty cycle			86%
T_min(on)	Minimum on-time			125		ns
I_Q-boost	Supply current in boost mode, no switching	EN/MODE = 1.6 V, FB = 1.4 V		5.2	9	mA
I_Q-SD	Supply current in shutdown mode	EN/MODE pin = 0.4 V		0.025	1	µA
I_Q-pass	Supply current in pass-through mode	EN/MODE = 2.6 V, FB = 1.4 V		1.4	2.3	mA
V_en-pass	Pass-through mode threshold⁽³⁾	Rising	2.19	2.4	2.56	V
V_mode-hyst	Mode change hysteresis, falling⁽³⁾	Falling	65	107	165	V
V_en-shutdown	Shutdown mode threshold⁽³⁾	Falling	0.2	0.4	0.59	V
V_en-boost	Boost mode enable window⁽³⁾	Rising	0.65	1.22	1.6	V
I_en	EN/MODE pin bias current⁽⁴⁾	EN/MODE = 1.6 V		±1		µA
V_SENSE	Cycle-by-cycle current limit threshold during boost mode	EN/MODE = 1.6 V, FB = 50 V	142	170	182	mV
ΔV_SC	Short-circuit current limit threshold during boost mode	EN/MODE = 1.6 V, FB = 0 V	18	30	42	mV
V_SL	Internal ramp compensation voltage			90		mV
V_LIM1	Input current limit threshold voltage in pass-through mode during T_LIM1⁽³⁾	EN/MODE = 2.6 V	70	85	95	mV
ΔV_LIM2	Input current limit threshold voltage in pass-through mode during T_LIM2⁽³⁾	EN/MODE = 2.6 V	14.5	18	21	mV
T_LIM1	Curent limit time at T_LIM1⁽³⁾			900		µs
T_LIM2	Current limit time at T_LIM2⁽³⁾			3.6		ms
T_SC	Current limit time at T_SC⁽³⁾			900		µs
V_OVP	Upper-output overvoltage protection threshold	Rising threshold measured at FB pin with respect to FB pin, VCOMP = 1.45 V		40		mV
V_OVP	Lower-output overvoltage protection threshold	Falling threshold measured at FB pin with respect to FB pin, VCOMP = 1.45 V		26		mV
V_GS-on	On-state drive voltage at VG pin⁽⁵⁾	V_IN= 5 V, ISEN = 5 V, I_G = 0 A	3.8	4.9		V
V_GS-off	Off-state drive voltage at VG pin⁽⁶⁾	Vin = 5 V, ISEN = V_IN – 200 mV, I_G = 0 A		5		mV
I_G	Maximum drive current at VG pin	V_IN = 5 V, ISEN = 5 V, V_G = V_IN		20		µA
G_m	Error amplifier transconductance	V_COM = 1.4 V, I_COMP = ±50 µA	340	522	900	µA/V
A_VOL	Error amplifier open-loop voltage gain	V_COM = 1.2 V to 1.8 V, I_COMP = 0 A	190	313	450	V/V
R_O	Error amplifier open-loop output resistance⁽⁷⁾			600		kΩ
I_EAO	Error amplifier output current swings	Sourcing: V_COMP = 1.4 V, V_FB = 1.1 V	27	66	115	µA
I_EAO	Error amplifier output current swings	Sinking: V_COMP = 1.4 V, V_FB = 1.4 V	49	68	125	µA
V_EAO	Error amplifier output voltage limits	Upper: V_FB = 0 V, COMP pin floating		2.3		V
V_EAO	Error amplifier output voltage limits	Lower: V_FB = 1.4 V		0.82		V
T_r	Drive pin rise time	C_load = 3 nF, V_DR = 0 V to 3 V		25		ns
T_f	Drive pin fall time	C_load = 3 nF, V_DR = 3 V to 0 V		25		ns
T_SD	Thermal shutdown threshold			165		°C
T_SD-hyst	Thermal shutdown threshold hysteresis			10		°C

(1) All limits are specified at room temperature and at temperature extremes. All room temperatures are 100% production tested. All limits at temperature extremes are specified through correlation using Statistical Quality Control (SQD) methods. All limits are used to calculate Average Outgoing Quaity Level (AOQL).

(2) Typical numbers are at 25°C and represent the most likely parametric norm.

(3) See Device Functional Modes and Overvoltage Protection.

(4) The bias current flowing through this pin is compensated and can flow either into or out-of this pin.

(5) This is the gate-to-source voltage drive of Q2, when the controller turns on this FET.

(6) This voltage is measured from the VG pin to AGND, when the controller fully turns off Q2.

(7) This parameter is calculated from the error amplified G_m and A_VOL, and is not tested.