Table 1. Design Parameters

8.2.2.1 External Capacitors

The output capacitor is critical to maintaining regulator stability, and must meet the required conditions for both ESR and minimum amount of capacitance.

8.2.2.2 Output Capacitor ESR

It is essential that the output capacitor meet the capacitance and ESR requirements, or oscillations can result. The ESR is used with the output capacitance in order to produce a zero in the control loop frequency response. This zero increases phase margin and ensures stability of the output voltage. Refer to ESR, Stability, and the LDO Regulator (SLVA115) for details.

Ceramic capacitors (MLCC) can be used for C_OUT only if a series resistor is added to simulate the ESR requirement. The ESR is not optional — it is mandatory. Typically, a 500-mΩ to 1-Ω series resistor is used for this purpose. When using MLCCs, due diligence must be given to initial tolerances, capacitance derating due to applied DC voltage, and capacitance variations due to temperature. Dielectric types X5R and X7R are preferred.

8.2.2.3 Power Dissipation

Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and load conditions and can be calculated with Equation 1.

Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available voltage drop option that would still be greater than the dropout voltage (V_DO). However, keep in mind that higher voltage drops result in better dynamic (that is, PSRR and transient) performance.

On the 8-pin SOIC (D) package, the four ground pins are thermally connected to the backside of the die. Adding approximately 0.04 square inches of 2 oz. copper pad area to these four pins improves the JEDEC R_θJA rating from 111.4°C/W to approximately 100°C/W. If this extra copper area is placed directly beneath the SOIC package there should not be any impact on board density.

Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (T_A), according to Equation 2 or Equation 2:

Unfortunately, this R_θJA is highly dependent on the heat-spreading capability of the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The R_θJA recorded in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copper-spreading area, and is to be used only as a relative measure of package thermal performance. For a well-designed thermal layout, R_θJA is actually the sum of the package junction-to-case (bottom) thermal resistance (R_θJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heat sink.

8.2.2.4 Estimating Junction Temperature

The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction temperatures of surface mount devices on a typical PCB board application. These characteristics are not true thermal resistance values, but rather package specific thermal characteristics that offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of copper-spreading area. The key thermal characteristics (Ψ_JT and Ψ_JB) are given in Thermal Information and are used in accordance with Equation 4 or Equation 5.

For more information about the thermal characteristics Ψ_JT and Ψ_JB, see Semiconductor and IC Package Thermal Metrics (SPRA953); for more information about measuring T_TOP and T_BOARD, see Using New Thermal Metrics (SBVA025); and for more information about the EIA/JEDEC JESD51 PCB used for validating R_θJA, see Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017). These application notes are available at www.ti.com.