ZHCSGD0 June   2017 LM25145

PRODUCTION DATA.  

1. 1 特性
2. 2 應用
3. 3 說明
4. 4 修訂歷史記錄
5. 5 說明 （續）
6. 6 Pin Configuration and Functions
   1. 6.1 Wettable Flanks
7. 7 Specifications
   1. 7.1 Absolute Maximum Ratings
   2. 7.2 ESD Ratings
   3. 7.3 Recommended Operating Conditions
   4. 7.4 Thermal Information
   5. 7.5 Electrical Characteristics
   6. 7.6 Switching Characteristics
   7. 7.7 Typical Characteristics
8. 8 Detailed Description
   1. 8.1 Overview
   2. 8.2 Functional Block Diagram
   3. 8.3 Feature Description
      1. 8.3.1  Input Range (VIN)
      2. 8.3.2  Output Voltage Setpoint and Accuracy (FB)
      3. 8.3.3  High-Voltage Bias Supply Regulator (VCC)
      4. 8.3.4  Precision Enable (EN/UVLO)
      5. 8.3.5  Power Good Monitor (PGOOD)
      6. 8.3.6  Switching Frequency (RT, SYNCIN)
         1. 8.3.6.1 Frequency Adjust
         2. 8.3.6.2 Clock Synchronization
      7. 8.3.7  Configurable Soft-Start (SS/TRK)
         1. 8.3.7.1 Tracking
      8. 8.3.8  Voltage-Mode Control (COMP)
      9. 8.3.9  Gate Drivers (LO, HO)
      10. 8.3.10 Current Sensing and Overcurrent Protection (ILIM)
      11. 8.3.11 OCP Duty Cycle Limiter
   4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
      4. 8.4.4 Diode Emulation Mode
      5. 8.4.5 Thermal Shutdown
9. 9 Application and Implementation
   1. 9.1 Application Information
      1. 9.1.1 Design and Implementation
      2. 9.1.2 Power Train Components
         1. 9.1.2.1 Inductor
         2. 9.1.2.2 Output Capacitors
         3. 9.1.2.3 Input Capacitors
         4. 9.1.2.4 Power MOSFETs
      3. 9.1.3 Control Loop Compensation
      4. 9.1.4 EMI Filter Design
   2. 9.2 Typical Applications
      1. 9.2.1 Design 1 - 20-A High-Efficiency Synchronous Buck Regulator for Telecom Power Applications
         1. 9.2.1.1 Design Requirements
         2. 9.2.1.2 Detailed Design Procedure
         3. 9.2.1.3 Custom Design With WEBENCH® Tools
         4. 9.2.1.4 Application Curves
      2. 9.2.2 Design 2 - High Density, 12-V, 8-A Rail With LDO Low-Noise Auxiliary Output for Industrial Applications
         1. 9.2.2.1 Design Requirements
         2. 9.2.2.2 Detailed Design Procedure
            1. 9.2.2.2.1 Application Curves
      3. 9.2.3 Design 3 - Powering a Multicore DSP From a 24-V Rail
         1. 9.2.3.1 Design Requirements
         2. 9.2.3.2 Detailed Design Procedure
         3. 9.2.3.3 Application Curves
10. 10Power Supply Recommendations
11. 11Layout
    1. 11.1 Layout Guidelines
       1. 11.1.1 Power Stage Layout
       2. 11.1.2 Gate Drive Layout
       3. 11.1.3 PWM Controller Layout
       4. 11.1.4 Thermal Design and Layout
       5. 11.1.5 Ground Plane Design
    2. 11.2 Layout Example
12. 12器件和文檔支持
    1. 12.1 器件支持
       1. 12.1.1 第三方產品免責聲明
       2. 12.1.2 開發支持
       3. 12.1.3 使用 WEBENCH® 工具定制設計方案
    2. 12.2 文檔支持
       1. 12.2.1 相關文檔
          1. 12.2.1.1 PCB 布局資源
          2. 12.2.1.2 熱設計資源
    3. 12.3 相關鏈接
    4. 12.4 接收文檔更新通知
    5. 12.5 社區資源
    6. 12.6 商標
    7. 12.7 靜電放電警告
    8. 12.8 Glossary
13. 13機械、封裝和可訂購信息