9.1.2.1 Inductor

For most applications, choose an inductance such that the inductor ripple current, ΔI_L, is between 30% and 40% of the maximum DC output current at nominal input voltage. Choose the inductance using Equation 7 based on a peak inductor current given by Equation 8.

Equation 7.

Equation 8.

Check the inductor datasheet to ensure that the saturation current of the inductor is well above the peak inductor current of a particular design. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low inductor core loss is evidenced by reduced no-load input current and higher light-load efficiency. However, ferrite core materials exhibit a hard saturation characteristic and the inductance collapses abruptly when the saturation current is exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple, not to mention reduced efficiency and compromised reliability. Note that the saturation current of an inductor generally deceases as its core temperature increases. Of course, accurate overcurrent protection is key to avoiding inductor saturation.

9.1.2.2 Output Capacitors

Ordinarily, the output capacitor energy store of the regulator combined with the control loop response are prescribed to maintain the integrity of the output voltage within the dynamic (transient) tolerance specifications. The usual boundaries restricting the output capacitor in power management applications are driven by finite available PCB area, component footprint and profile, and cost. The capacitor parasitics—equivalent series resistance (ESR) and equivalent series inductance (ESL)—take greater precedence in shaping the load transient response of the regulator as the load step amplitude and slew rate increase.

The output capacitor, C_OUT, filters the inductor ripple current and provides a reservoir of charge for step-load transient events. Typically, ceramic capacitors provide extremely low ESR to reduce the output voltage ripple and noise spikes, while tantalum and electrolytic capacitors provide a large bulk capacitance in a relatively compact footprint for transient loading events.

Based on the static specification of peak-to-peak output voltage ripple denoted by ΔV_OUT, choose an output capacitance that is larger than that given by Equation 9.

Equation 9.

Figure 42 conceptually illustrates the relevant current waveforms during both load step-up and step-down transitions. As shown, the large-signal slew rate of the inductor current is limited as the inductor current ramps to match the new load-current level following a load transient. This slew-rate limiting exacerbates the deficit of charge in the output capacitor, which must be replenished as rapidly as possible during and after the load step-up transient. Similarly, during and after a load step-down transient, the slew rate limiting of the inductor current adds to the surplus of charge in the output capacitor that must be depleted as quickly as possible.

Figure 42. Load Transient Response Representation Showing C_OUT Charge Surplus or Deficit

In a typical regulator application of 24-V input to low output voltage (for example, 5 V), it should be recognized that the load-off transient represents worst-case. In that case, the steady-state duty cycle is approximately 10% and the large-signal inductor current slew rate when the duty cycle collapses to zero is approximately –V_OUT/L. Compared to a load-on transient, the inductor current takes much longer to transition to the required level. The surplus of charge in the output capacitor causes the output voltage to significantly overshoot. In fact, to deplete this excess charge from the output capacitor as quickly as possible, the inductor current must ramp below its nominal level following the load step. In this scenario, a large output capacitance can be advantageously employed to absorb the excess charge and limit the voltage overshoot.

To meet the dynamic specification of output voltage overshoot during such a load-off transient (denoted as ΔV_OVERSHOOT with step reduction in output current given by ΔI_OUT), the output capacitance should be larger than

Equation 10.

The ESR of a capacitor is provided in the manufacturer’s data sheet either explicitly as a specification or implicitly in the impedance vs. frequency curve. Depending on type, size and construction, electrolytic capacitors have significant ESR, 5 mΩ and above, and relatively large ESL, 5 nH to 20 nH. PCB traces contribute some parasitic resistance and inductance as well. Ceramic output capacitors, on the other hand, have low ESR and ESL contributions at the switching frequency, and the capacitive impedance component dominates. However, depending on package and voltage rating of the ceramic capacitor, the effective capacitance can drop quite significantly with applied DC voltage and operating temperature.

Ignoring the ESR term in Equation 9 gives a quick estimation of the minimum ceramic capacitance necessary to meet the output ripple specification. One to four 47-µF, 10-V, X7R capacitors in 1206 or 1210 footprint is a common choice. Use Equation 10 to determine if additional capacitance is necessary to meet the load-off transient overshoot specification.

A composite implementation of ceramic and electrolytic capacitors highlights the rationale for paralleling capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range. While the ceramic provides excellent mid- and high-frequency decoupling characteristics with its low ESR and ESL to minimize the switching frequency output ripple, the electrolytic device with its large bulk capacitance provides low-frequency energy storage to cope with load transient demands.

9.1.2.3 Input Capacitors

Input capacitors are necessary to limit the input ripple voltage to the buck power stage due to switching-frequency AC currents. TI recommends using X5R or X7R dielectric ceramic capacitors to provide low impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance in the switching loop, position the input capacitors as close as possible to the drain of the high-side MOSFET and the source of the low-side MOSFET. The input capacitor RMS current is given by Equation 11.

Equation 11.

The highest input capacitor RMS current occurs at D = 0.5, at which point the RMS current rating of the capacitors should be greater than half the output current.

Ideally, the DC component of input current is provided by the input voltage source and the AC component by the input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude (I_OUT − I_IN) during the D interval and sinks I_IN during the 1−D interval. Thus, the input capacitors conduct a square-wave current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, the peak-to-peak ripple voltage amplitude is given by Equation 12.

Equation 12.

The input capacitance required for a particular load current, based on an input voltage ripple specification of ΔV_IN, is given by Equation 13.

Equation 13.

Low-ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating with high-Q ceramics. One bulk capacitor of sufficiently high current rating and two or three 2.2-μF 100-V X7R ceramic decoupling capacitors are usually sufficient. Select the input bulk capacitor based on its ripple current rating and operating temperature.

9.1.2.4 Power MOSFETs

The choice of power MOSFETs has significant impact on DC-DC regulator performance. A MOSFET with low on-state resistance, R_DS(on), reduces conduction loss, whereas low parasitic capacitances enable faster transition times and reduced switching loss. Normally, the lower the R_DS(on) of a MOSFET, the higher the gate charge and output charge (Q_G and Q_OSS respectively), and vice versa. As a result, the product R_DS(on) × Q_G is commonly specified as a MOSFET figure-of-merit. Low thermal resistance ensures that the MOSFET power dissipation does not result in excessive MOSFET die temperature.

The main parameters affecting power MOSFET selection in an LM25145 application are as follows:

• R_DS(on) at V_GS = 7.5 V;
• Drain-source voltage rating, BV_DSS, typically 30 V, 40 V or 60 V, depending on maximum input voltage;
• Gate charge parameters at V_GS = 7.5 V;
• Output charge, Q_OSS, at the relevant input voltage;
• Body diode reverse recovery charge, Q_RR;
• Gate threshold voltage, V_GS(th), derived from the plateau in the Q_G vs. V_GS plot in the MOSFET data sheet. With a MOSFET Miller plateau voltage typically in the range of 3 V to 5 V, the 7.5-V gate drive amplitude of the LM25145 provides an adequately-enhanced MOSFET when on and a margin against Cdv/dt shoot-through when off.

The MOSFET-related power losses are summarized by the equations presented in Table 2, where suffixes 1 and 2 represent high-side and low-side MOSFET parameters, respectively. While the influence of inductor ripple current is considered, second-order loss modes, such as those related to parasitic inductances and SW node ringing, are not included. Consult the LM25145 Quickstart Calculator to assist with power loss calculations.

Table 2. Buck Regulator MOSFET Power Losses

POWER LOSS MODE	HIGH-SIDE MOSFET	LOW-SIDE MOSFET
MOSFET Conduction(2)(3)
MOSFET Switching		Negligible
MOSFET Gate Drive(1)
MOSFET Output Charge(4)
Body Diode Conduction	N/A
Body Diode Reverse Recovery(5)

(1) Gate drive loss is apportioned based on the internal gate resistance of the MOSFET, externally-added series gate resistance and the relevant driver resistance of the LM25145.

(2) MOSFET R_DS(on) has a positive temperature coefficient of approximately 4500 ppm/°C. The MOSFET junction temperature, T_J, and its rise over ambient temperature is dependent upon the device total power dissipation and its thermal impedance.

(3) D' = 1–D is the duty cycle complement.

(4) MOSFET output capacitances, C_oss1 and C_oss2, are highly non-linear with voltage. These capacitances are charged losslessly by the inductor current at high-side MOSFET turn-off. During turn-on, however, a current flows from the input to charge the output capacitance of the low-side MOSFET. E_oss1, the energy of C_oss1, is dissipated at turn-on, but this is offset by the stored energy E_oss2 on C_oss2.

(5) MOSFET body diode reverse recovery charge, Q_RR, depends on many parameters, particularly forward current, current transition speed and temperature.

The high-side (control) MOSFET carries the inductor current during the PWM on-time (or D interval) and typically incurs most of the switching losses. It is therefore imperative to choose a high-side MOSFET that balances conduction and switching loss contributions. The total power dissipation in the high-side MOSFET is the sum of the losses due to conduction, switching (voltage-current overlap), output charge, and typically two-thirds of the net loss attributed to body diode reverse recovery.

The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or 1–D interval). The low-side MOSFET switching loss is negligible as it is switched at zero voltage – current just commutates from the channel to the body diode or vice versa during the transition dead-times. The LM25145, with its adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such losses scale directly with switching frequency.

In high step-down ratio applications, the low-side MOSFET carries the current for a large portion of the switching period. Therefore, to attain high efficiency, it is critical to optimize the low-side MOSFET for low R_DS(on). In cases where the conduction loss is too high or the target R_DS(on) is lower than available in a single MOSFET, connect two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode reverse recovery. The LM25145 is well suited to drive TI's comprehensive portfolio of NexFET™ power MOSFETs.

Table 3. Buck Regulator Poles and Zeros⁽¹⁾⁽²⁾

POWER STAGE POLES	POWER STAGE ZEROS	COMPENSATOR POLES	COMPENSATOR ZEROS

Table 4. Buck Regulator Small-Signal Analysis

TRANSFER FUNCTION	EXPRESSION
Open-loop transfer function
Duty-cycle-to-output transfer function
Compensator transfer function(1)
Modulator transfer function

Table 5. Compensation Component Selection

RESISTORS	CAPACITORS

9.2.1.1 Design Requirements

The intended input, output, and performance-related parameters pertinent to this design example are shown in Table 6.

9.2.1.2 Detailed Design Procedure

The design procedure for an LM25145-based regulator for a given application is streamlined by using the LM25145 Quickstart Calculator available as a free download, or by availing of TI's WEBENCH® Power Designer.

The selected buck converter powertrain components are cited in Table 7, and many of the components are available from multiple vendors. The MOSFETs in particular are chosen for both lowest conduction and switching power loss, as discussed in detail in Power MOSFETs.

The current limit setpoint in this design is set at 26 A based on the resistor R_ILIM and the 2-mΩ R_DS(on) of the low-side MOSFET (typical at T_J = 25°C and V_GS = 7.5 V). This design uses a low-DCR, metal-powder inductor and an all-ceramic output capacitor implementation.

9.2.1.3 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM25145 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.1.4 Application Curves

SYNCIN tied to VCC

Figure 47. Efficiency and Power Loss vs I_OUT and V_IN, CCM

VIN step to 24 V

0.25-Ω Load

Figure 49. Start-Up, 20-A Resistive Load

VIN = 24 V

0.25-Ω Load

Figure 51. ENABLE ON, 20-A Resistive Load

VIN = 24 V

Figure 53. Load Transient Response, 10 A to 20 A to 10 A

VIN = 24 V

IOUT = 0 A

Figure 55. SYNCOUT and SW Node Voltages

SYNCIN tied to GND

Figure 48. Efficiency and Power Loss vs I_OUT and V_IN, DCM

VIN 24 V to 6 V

0.25-Ω Load

Figure 50. Shutdown Through Input UVLO, 20-A Resistive Load

VIN = 24 V

0.25-Ω Load

Figure 52. ENABLE OFF, 20-A Resistive Load

VIN = 24 V

Figure 54. Load Transient Response, 0 A to 20 A to 0 A

VIN = 24 V

IOUT = 20 A

Figure 56. SW Node Voltage

9.2.2.1 Design Requirements

The required input, output, and performance parameters for this application example are shown in Table 8.

9.2.2.2 Detailed Design Procedure

A high power density, high-efficiency regulator solution is realized by using TI NexFET™ Power MOSFETs, such as CSD18543Q3A (60-V, 8.5-mΩ MOSFET in a SON 3.3-mm × 3.3-mm package), together with a low-DCR inductor and all-ceramic capacitor design. The design occupies 15 mm × 15 mm on a single-sided PCB. The overcurrent (OC) setpoint in this design is set at 11 A based on the resistor R_ILIM and the 8.5-mΩ R_DS(on) of the low-side MOSFET (typical at T_J = 25°C and V_GS = 7.5 V). Connecting VCC to either V_OUT1 or V_OUT2 using a series diode reduces bias power dissipation and improves efficiency, especially at light loads.

The selected buck converter powertrain components are cited in Table 9, including power MOSFETs, buck inductor, input and output capacitors, and ICs. Using the LM25145 Quickstart Calculator, compensation components are selected based on a target loop crossover frequency of 70 kHz and phase margin greater than 55°. The output voltage soft-start time is 4 ms based on the selected soft-start capacitance, C_SS, of 47 nF.

If needed, a 2.2-Ω resistor can be added in series with C_BST is used to slow the turn-on transition of the high-side MOSFET, reducing the spike amplitude and ringing of the SW node voltage and minimizing the possibility of Cdv/dt-induced shoot-through of the low-side MOSFET. If needed, place an RC snubber (for example, 2.2 Ω and 100 pF) close to the drain (SW node) and source (PGND) terminals of the low-side MOSFET to further attenuate any SW node voltage overshoot and/or ringing. Please refer to the application note Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics for more detail.

9.2.2.2.1 Application Curves

Figure 58. Efficiency vs I_OUT and V_IN

VIN step to 24 V

1.5-Ω Load

Figure 60. Start-Up, 8-A Resistive Load

VIN = 24 V

1.5-Ω Load

Figure 62. ENABLE ON, 8-A Resistive Load

VIN = 24 V

IOUT = 0 A

Figure 64. Pre-Biased Start-Up

VIN = 24 V

Figure 66. Load Transient Response, 4 A to 8 A to 4 A

IOUT = 8 A

Figure 68. Line Transient Response, 18 V to 36 V

VIN = 24 V

IOUT = 4 A

Figure 59. SYNCOUT and SW Node Voltages

1.5-Ω Load

Figure 61. Shutdown Through Input UVLO, 8-A Resistive Load

VIN = 24 V

1.5-Ω Load

Figure 63. ENABLE OFF, 8-A Resistive Load

VIN = 24 V

IOUT = 0 A

Figure 65. SW Node and VOUT Ripple

VIN = 24 V

Figure 67. Load Transient Response, 0.8 A to 8 A to 0.8 A

IOUT = 8 A

Figure 69. Line Transient Response, 36 V to 18 V

9.2.3.1 Design Requirements

For this application example, the intended input, output, and performance parameters are listed in Table 10.

9.2.3.2 Detailed Design Procedure

The schematic diagram of a 300-kHz, 24-V nominal input, 10-A regulator powering a KeyStone™ DSP is given in Figure 70. This high step-down ratio design leverages the low 40-ns minimum controllable on-time of the LM25145 controller to achieve stable, efficient operation at very low duty cycles. 60-V power MOSFETs, such as TI's CSD18543Q3A and CSD18531Q5A NexFET devices, are used together with a low-DCR, metal-powder inductor, and ceramic output capacitor implementation. An external rail between 8 V and 13 V powers VCC to minimize bias power dissipation, and a blocking diode connected to the VIN pin is used as recommended in Figure 32.

The important components for this design are listed in Table 11.

The regulator output current requirements are dependent upon the baseline and activity power consumption of the DSP in a real-use case. While baseline power is highly dependent on voltage, temperature and DSP frequency, activity power relates to dynamic core utilization, DDR3 memory access, peripherals, and so on. To this end, the IDAC_OUT pin of the LM10011 connects to the LM25145 FB pin to allow continuous optimization of the core voltage. The SmartReflex-enabled DSP provides 6-bit information using the VCNTL open-drain I/Os to command the output voltage setpoint with 6.4-mV step resolution.⁽¹⁾

9.2.3.3 Application Curves

VOUT = 1.1 V

VAUX = 8 V

Figure 71. Efficiency vs I_OUT and V_IN

VIN = 24 V

0.11-Ω Load

Figure 73. ENABLE ON and OFF, 10-A Resistive Load

VIN step to 24 V

0.11-Ω Load

Figure 72. Start-Up, 10-A Resistive Load

VIN = 24 V

Figure 74. Load Transient Response, 0 A to 10 A to 0 A