With the proviso to locate the controller
close to the power MOSFETs and minimize gate driver trace runs, the following considers
components related to the analog and feedback signals as well as current sensing:
- Separate power and signal traces, and
use a ground plane to provide noise shielding.
- Place all sensitive analog traces and
components related to COMP1/2, FB1/2, ISNS1/2+, RSS, and RT away from high-voltage
switching nodes such as SW1/2, HO1/2, LO1/2 or CBOOT1/2 to avoid mutual coupling. Use
internal layers as ground planes. Pay particular attention to shielding the feedback
(FB) trace from power traces and components.
- Locate the upper and lower feedback
resistors (if required) close to the respective FB pins, keeping the FB traces as short
as possible. Route the trace from the upper feedback resistors to the required output
voltage sense points at the loads.
- Route the [ISNS1+, BIAS1/VOUT1] and
[ISNS2+, VOUT1/2] traces as differential pairs to minimize noise pickup and use Kelvin
connections to the applicable shunt resistor (if shunt current sensing is used) or to
the sense capacitor (if inductor DCR current sensing is used). In particular, use a
wide trace for the connection to BIAS1/VOUT1, preferably 80mils (2mm), to minimize
the voltage drop related to bias current flowing to that pin affecting the current
sense.
- Minimize the loop area from the VCC and
VIN pins through the respective decoupling capacitors to the PGND pin. Locate these
capacitors as close as possible to the LM25137.