Noise coupling of the high frequency switching between two channels through the input power rail
Maintain the high current path as short as possible
Choose a FET with minimum lead inductance
Place local bypass capacitors (CIN1, CIN2) as close as possible to the high-side FETs to isolate one channel from the high frequency noise of the other channel
Slow down the SW switching speed by increasing gate resistors R29 and R30
Minimize the effective ESR or ESL of the input capacitor by paralleling input capacitors
High frequency AC noise on FB, CS, CSG and COMP
Use the star ground PCB layout technique and minimize the length of the high current path
Place the signal traces away from the SW, HO, HB traces and the inductor
Add an R-C filter between the CS and CSG pins
Place CS filter capacitor (C30, C31) next to the LM25119 and on the same PCB layer as the LM25119
Ground offset at the switching frequency
Use the star ground PCB layout technique and minimize the length between the grounds of CIN1 and CIN2