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SNVS700G December 2010 – October 2016 LM25066A

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

NHZ|24
- MPQS005

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

8 Detailed Description

8.1 Overview

The inline protection functionality of the LM25066A is designed to control the in-rush current to the load upon insertion of a circuit card into a live backplane or other hot power source, thereby limiting the voltage sag on the backplane's supply voltage and the dV/dt of the voltage applied to the load. Effects on other circuits in the system are minimized, preventing possible unintended resets. A controlled shutdown when the circuit card is removed can also be implemented using the LM25066A.

In addition to a programmable current limit, the LM25066A monitors and limits the maximum power dissipation in the series pass device to maintain operation within the device Safe Operating Area (SOA). Either current limiting or power limiting for an extended period of time results in the shutdown of the series pass device. In this event, the LM25066A can latch off or repetitively retry based on the hardware setting of the RETRY pin. Once started, the number of retries can be set to none, 1, 2, 4, 8, 16, or infinite. The circuit breaker function quickly switches off the series pass device upon detection of a severe overcurrent condition. Programmable undervoltage lockout (UVLO) and overvoltage lockout (OVLO) circuits shut down the LM25066A when the system input voltage is outside the desired operating range.

The telemetry capability of the LM25066A provides intelligent monitoring of the input voltage, output voltage, input current, input power, temperature, and an auxiliary input. The LM25066A also provides a peak capture of the input power and programmable hardware averaging of the input voltage, current, power, and output voltage. Warning thresholds which trigger the SMBA pin may be programmed for input and output voltage, current, power and temperature via the PMBus interface. Additionally, the LM25066A is capable of detecting damage to the external MOSFET, Q₁.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Current Limit

The current limit threshold is reached when the voltage across the sense resistor R_S (VIN to SENSE) exceeds the internal voltage limit of 25 mV or 46 mV depending on whether the CL pin is connected to GND or VDD, respectively. In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q₁. While the current limit circuit is active, the fault timer is active as described in Fault Timer and Restart. If the load current falls below the current limit threshold before the end of the Fault Timeout Period, the LM25066A resumes normal operation. If the current limit condition persists for longer than the Fault Timeout Period set by the timer capacitor, C_T, the IIN OC FAULT bit in the MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h) register, the INPUT bit in the STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in the register will be toggled high and SMBA pin will be pulled low unless this feature is disabled using the MFR_SPECIFIC_08: ALERT_MASK (D8h) register. For proper operation, the R_S resistor value should be less than 200 mΩ. Higher values may create instability in the current limit control loop. The current limit threshold pin value may be overridden by setting appropriate bits in the MFR_SPECIFIC_09: DEVICE_SETUP (D9h).

8.3.2 Circuit Breaker

If the load current increases rapidly (for example, the load is short-circuited), the current in the sense resistor (R_S) may exceed the current limit threshold before the current limit control loop is able to respond. If the current exceeds 1.8 or 3.6 times (user settable) the current limit threshold, Q₁ is quickly switched off by the 190-mA pulldown current at the GATE pin, and a Fault Timeout Period begins. When the voltage across R_S falls below the threshold the 190-mA pulldown current at the GATE pin is switched off and the gate voltage of Q₁ is then determined by the current limit or power limit functions. If the TIMER pin reaches 1.7 V before the current limiting or power limiting condition ceases, Q₁ is switched off by the 2-mA pulldown current at the GATE pin as described in Fault Timer and Restart. A circuit breaker event will cause the CIRCUIT BREAKER FAULT bit in the STATUS_MFR_SPECIFIC (80h) and MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h) registers to be toggled high and SMBA pin will be pulled low unless this feature is disabled using the MFR_SPECIFIC_08: ALERT_MASK (D8h) register. The circuit breaker pin configuration may be overridden by setting appropriate bits in the MFR_SPECIFIC_09: DEVICE_SETUP (D9h)) register.

8.3.3 Power Limit

An important feature of the LM25066A is the MOSFET power limiting. The Power Limit function can be used to maintain the maximum power dissipation of MOSFET Q₁ within the device SOA rating. The LM25066A determines the power dissipation in Q₁ by monitoring its drain-source voltage (SENSE to OUT), and the drain current through R_S (VIN to SENSE). The product of the current and voltage is compared to the power limit threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the GATE voltage is controlled to regulate the current in Q₁. While the power limiting circuit is active, the fault timer is active as described in Fault Timer and Restart. If the power limit condition persists for longer than the Fault Timeout Period set by the timer capacitor, C_T, the IIN_OC_FAULT bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in theMFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h) register will be toggled high and SMBA pin will be pulled low unless this feature is disabled using the MFR_SPECIFIC_08: ALERT_MASK (D8h) register.

8.3.4 Undervoltage Lockout (UVLO)

The series pass MOSFET (Q₁) is enabled when the input supply voltage (V_SYS) is within the operating range defined by the programmable undervoltage lockout (UVLO) and overvoltage lockout (OVLO) levels. Typically the UVLO level at V_SYS is set with a resistor divider (R1-R3) as shown in Figure 35. Refering to the Block Diagram when V_SYS is below the UVLO level, the internal 23-µA current source at UVLO is enabled, the current source at OVLO is off, and Q₁ is held off by the 2-mA pulldown current at the GATE pin. As V_SYS is increased, raising the voltage at UVLO above its threshold the 23-µA current source at UVLO is switched off, increasing the voltage at UVLO, providing hysteresis for this threshold. With the UVLO/EN pin above its threshold, Q₁ is switched on by the 22-µA current source at the GATE pin if the insertion time delay has expired.

See Typical Application for a procedure to calculate the values of the threshold setting resistors (R1-R3). The minimum possible UVLO level at V_SYS can be set by connecting the UVLO/EN pin to VIN. In this case, Q₁ is enabled after the insertion time when the voltage at VIN reaches the POR threshold. After power up, an UVLO condition will toggle high the VIN UV FAULT bit in the STATUS_INPUT (7Ch), the INPUT bit in the STATUS_WORD (79h) register, and the VIN_UNDERVOLTAGE_FAULT bit in the MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h) register, and SMBA pin will be pulled low unless this feature is disabled using the MFR_SPECIFIC_08: ALERT_MASK (D8h) register.

8.3.5 Overvoltage Lockout (OVLO)

The series pass MOSFET (Q₁) is enabled when the input supply voltage (V_SYS) is within the operating range defined by the programmable undervoltage lockout (UVLO) and overvoltage lockout (OVLO) levels. If V_SYS raises the OVLO pin voltage above its threshold, Q₁ is switched off by the 2-mA pulldown current at the GATE pin, denying power to the load. When the OVLO pin is above its threshold, the internal 23 µA current source at OVLO is switched on, raising the voltage at OVLO to provide threshold hysteresis. When V_SYS is reduced below the OVLO level, Q₁ is re-enabled. An OVLO condition will toggle high the VIN OV FAULT bit in the STATUS_INPUT (7Ch), the INPUT bit in the STATUS_WORD (79h) register, and the VIN_OVERVOLTAGE_FAULT bit in the MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h) register, and the SMBA pin will be pulled low unless this feature is disabled using the MFR_SPECIFIC_08: ALERT_MASK (D8h) register.

See Typical Application for a procedure to calculate the threshold setting resistor values.

8.3.6 Power Good

The Power Good indicator (PGD) is connected to the drain of an internal N-channel MOSFET capable of sustaining 17 V in the off-state, and transients up to 20 V. An external pullup resistor is required at PGD to an appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be higher or lower than the voltages at VIN and OUT. PGD is switched high when the voltage at the FB pin exceeds the PGD threshold voltage. Typically, the output voltage threshold is set with a resistor divider from output to feedback, although the monitored voltage need not be the output voltage. Any other voltage can be monitored as long as the voltage at the FB pin does not exceed its maximum rating. Referring to the Block Diagram, when the voltage at the FB pin is below its threshold, the 24-µA current source at FB is disabled. As the output voltage increases, taking FB above its threshold, the current source is enabled, sourcing current out of the pin, raising the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either the UVLO/EN pin is below its threshold or the OVLO pin is above its threshold. The status of the PGD pin can be read via the PMBus interface in either the STATUS_WORD (79h) or MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h) registers.

8.3.7 VDD Sub-Regulator

The LM25066A contains an internal linear sub-regulator which steps down the input voltage to generate a 4.5 V rail used for powering low voltage circuitry. When the input voltage is below 4.5 V, VDD will track VIN. For input voltages 3.3 V and below, VDD should be tied directly to VIN to avoid the dropout of the sub-regulator. The VDD sub-regulator should be used as the pullup supply for the CL, CB, RETRY, ADR2, ADR1, ADR0 pins if they are to be tied high. It may also be used as the pullup supply for the PGD and the SMBus signals (SDA, SCL, SMBA). The VDD sub-regulator is not designed to drive high currents and should not be loaded with other integrated circuits. The VDD pin is current limited to 45 mA in order to protect the LM25066A in the event of a short. The sub-regulator requires a bypass capacitance having a value from 1 µF to 4.7 µF to be placed as close to the VDD pin as the PCB layout allows.

8.3.8 Remote Temperature Sensing

The LM25066A is designed to measure temperature remotely using an MMBT3904 NPN transistor. The base and collector of the MMBT3904 is connected to the DIODE pin and the emitter is grounded. Place the MMBT3904 near the device whose temperature is to be monitored. If the temperature of the hot-swap pass MOSFET, Q₁, is to be measured, the MMBT3904 should be placed as close to Q₁ as the layout allows. The temperature is measured by means of a change in the diode voltage in response to a step in current supplied by the DIODE pin. The DIODE pin sources a constant 9.4 µA but pulses 250 µA once every millisecond in order to measure the diode temperature. Care must be taken in the PCB layout to keep the parasitic resistance between the DIODE pin and the MMBT3904 low so as not to degrade the measurement. Additionally, a small 1000-pF bypass capacitor should be placed in parallel with the MMBT3904 to reduce the effects of noise. The temperature can be read using the READ_TEMPERATURE_1 (8Dh) PMBus command. The default limits of the LM25066A will cause SMBA pin to be pulled low if the measured temperature exceeds 125°C and will disable the hot-swap pass MOSFET if the temperature exceeds 150°C. These thresholds can be reprogrammed via the PMBus interface using the OT_WARN_LIMIT (51h) and OT_FAULT_LIMIT (4Fh) commands. If the temperature measurement and protection capability of the LM25066A is not used, the DIODE pin should be grounded.

8.3.9 Damaged MOSFET Detection

The LM25066A is able to detect whether the external MOSFET, Q₁, is damaged under certain conditions. If the voltage across the sense resistor exceeds 4 mV while the GATE voltage is low or the internal logic indicates that the GATE should be low, the EXT_MOSFET_SHORTED bit in the STATUS_MFR_SPECIFIC (80h) and MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h) registers will be toggled high and the SMBA pin will be pulled low unless this feature is disabled using the MFR_SPECIFIC_08: ALERT_MASK (D8h). This method effectively determines whether Q₁ is shorted because of damage present between the drain and gate and/or drain and source of the external MOSFET.

8.4 Device Functional Modes

8.4.1 Power Up Sequence

The VIN operating range of the LM25066A is +2.9 V to +17 V, with transient capability to +24 V. Referring to Figure 38 and Figure 32, as the voltage at VIN initially increases, the external N-channel MOSFET (Q₁) is held off by an internal 190-mA pulldown current at the GATE pin. The strong pulldown current at the GATE pin prevents an inadvertent turnon as the MOSFET's gate-to-drain (Miller) capacitance is charged. Additionally, the TIMER pin is initially held at ground. When the V_IN voltage reaches the POR threshold, the insertion time begins. During the insertion time, the capacitor at the TIMER pin (C_T) is charged by a 5.5-µA current source and Q₁ is held off by a 2-mA pulldown current at the GATE pin regardless of the input voltage. The insertion time delay allows ringing and transients at VIN to settle before Q₁ is enabled. The insertion time ends when the TIMER pin voltage reaches 1.7 V. C_T is then quickly discharged by an internal 1.9-mA pulldown current. The GATE pin then switches on Q₁ when V_SYS, the input supply voltage, exceeds the UVLO threshold. If V_SYS is above the UVLO threshold at the end of the insertion time, Q₁ switches on at that time. The GATE pin charge pump sources 22 µA to charge the gate capacitance of Q₁. The maximum voltage at the GATE pin with respect to ground is limited by an internal 18.8-V Zener diode.

As the voltage at the OUT pin increases, the LM25066A monitors the drain current and power dissipation of MOSFET Q₁. Inrush current limiting and/or power limiting circuits actively control the current delivered to the load. During the inrush limiting interval (t₂ in Figure 32), an internal 90-A fault timer current source charges C_T. If Q₁'s power dissipation and the input current reduce below their respective limiting thresholds before the TIMER pin reaches 1.7 V, the 90-µA current source is switched off and C_T is discharged by the internal 2.8-µA current sink (t₃ in Figure 32). The PGD pin switches high when FB exceeds its rising threshold of 1.167 V.

If the TIMER pin voltage reaches 1.7 V before inrush current limiting or power limiting ceases during t₂, a fault is declared and Q₁ is turned off. See Fault Timer and Restart for a complete description of the fault mode.

The LM25066A will pull the SMBA pin low after the input voltage has exceeded its POR threshold to indicate that the volatile memory and device settings are in their default state. The CONFIG_PRESET bit within the STATUS_MFR_SPECIFIC (80h) indicates default configuration of warning thresholds and device operation and will remain set until a CLEAR_FAULTS command is received.

Figure 32. Power Up Sequence (Current Limit Only)

8.4.2 Gate Control

A charge pump provides the voltage at the GATE pin to enhance the N-Channel MOSFET's gate. During normal operating conditions (t₃ in Figure 32) the gate of Q₁ is held charged by an internal 22-µA current source. The voltage at the GATE pin (with respect to ground) is limited by an internal 18.8-V Zener diode. See Figure 7. Since the gate-to-source voltage applied to Q₁ could be as high as 18.8 V during various conditions, a Zener diode with the appropriate voltage rating must be added between the GATE and OUT pins if the maximum V_GS rating of the selected MOSFET is less than 18.8 V. The external Zener diode must have a forward current rating of at least 190 mA. When the system voltage is initially applied, the GATE pin is held low by a 190-mA pulldown current. This helps prevent an inadvertent turnon of the MOSFET through its drain-gate capacitance as the applied system voltage increases.

During the insertion time (t₁ in Figure 32) the GATE pin is held low by a 2-mA pulldown current. This maintains Q₁ in the off-state until the end of t₁, regardless of the voltage at VIN or UVLO. Following the insertion time (t₂ in Figure 32), the gate voltage of Q₁ is controlled to keep the current or power dissipation level from exceeding the programmed levels. While in the current or power limiting mode, the TIMER pin capacitor is charging. If the current and power limiting cease before the TIMER pin reaches 1.7 V, the TIMER pin capacitor then discharges, and the circuit begins normal operation. If the inrush limiting condition persists such that the TIMER pin reached 1.7 V during t₂, the GATE pin is then pulled low by the 190-mA pulldown current. The GATE pin is then held low until either a power up sequence is initiated (RETRY pin to VDD), or an automatic retry is attempted (RETRY pin to GROUND). See Fault Timer and Restart. If the system input voltage falls below the UVLO threshold or rises above the OVLO threshold, the GATE pin is pulled low by the 2-mA pulldown current to switch off Q₁.

8.4.3 Fault Timer and Restart

When the current limit or power limit threshold is reached during turnon, or as a result of a fault condition, the gate-to-source voltage of Q₁ is controlled to regulate the load current and power dissipation in Q₁. When either limiting function is active, a 90-µA fault timer current source charges the external capacitor (C_T) at the TIMER pin as shown in Figure 32 (Fault Timeout Period). If the fault condition subsides during the Fault Timeout Period before the TIMER pin reaches 1.7 V, the LM25066A returns to the normal operating mode and C_T is discharged by the 1.9-mA current sink. If the TIMER pin reaches 1.7 V during the Fault Timeout Period, Q₁ is switched off by a 2-mA pulldown current at the GATE pin. The subsequent restart procedure then depends on the selected retry configuration.

If the RETRY pin is high, the LM25066A latches the GATE pin low at the end of the Fault Timeout Period. C_T is then discharged to ground by the 2.8-µA fault current sink. The GATE pin is held low by the 2-mA pulldown current until a power up sequence is externally initiated by cycling the input voltage (V_SYS), or momentarily pulling the UVLO/EN pin below its threshold with an open-collector or open-drain device as shown in Figure 33. The voltage at the TIMER pin must be <0.3 V for the restart procedure to be effective. The TIMER_LATCHED_OFF bit in the MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h) register will remain high while the latched off condition persists.

LM25066A Latched_Fault_Reset_Control.gif

Figure 33. Latched Fault Restart Control

The LM25066A provides an automatic restart sequence which consists of the TIMER pin cycling between 1.7 V and 1 V seven times after the Fault Timeout Period, as shown in Figure 34. The period of each cycle is determined by the 90-µA charging current, and the 2.8-µA discharge current, and the value of the capacitor C_T. When the TIMER pin reaches 0.3 V during the eighth high-to-low ramp, the 22-µA current source at the GATE pin turns on Q₁. If the fault condition is still present, the Fault Timeout Period and the restart sequence repeat. The RETRY pin allows selecting no retries or infinite retries. Finer control of the retry behavior can be achieved through the MFR_SPECIFIC_09: DEVICE_SETUP (D9h) register. Retry counts of 0, 1, 2, 4, 8, 16 or infinite may be selected by setting the appropriate bits in the MFR_SPECIFIC_09: DEVICE_SETUP (D9h) register.

Figure 34. Restart Sequence

8.4.4 Shutdown Control

The load current can be remotely switched off by taking the UVLO/EN pin below its threshold with an open collector or open drain device, as shown in Figure 35. Upon releasing the UVLO/EN pin, the LM25066A switches on the load current with inrush current and power limiting.

Figure 35. Shutdown Control

8.4.5 Enabling/Disabling and Resetting

The output can be disabled at any time during normal operation by either pulling the UVLO/EN pin to below its threshold or the OVLO pin above its threshold, causing the GATE voltage to be forced low with a pulldown strength of 2 mA. Toggling the UVLO/EN pin will also reset the LM25066A from a latched-off state due to an overcurrent or over-power limit condition which has caused the maximum allowed number of retries to be exceeded. While the UVLO/EN or OVLO pins can be used to disable the output, they have no effect on the volatile memory or address location of the LM25066A. User stored values for address, device operation, and warning and fault levels programmed via the SMBus are preserved while the LM25066A is powered regardless of the state of the UVLO/EN and OVLO pins. The output may also be enabled or disabled by writing 80h or 0h to the OPERATION (03h) register. To re-enable after a fault, the fault condition should be cleared and the OPERATION (03h) register should be written to 0h and then 80h.

The SMBus address of the LM25066A is captured based on the states of the ADR0, ADR1, and ADR2 pins (GND, NC, VDD) during turnon and is latched into a volatile register once VDD has exceeded its POR threshold of 2.6 V. Reassigning or postponing the address capture is accomplished by holding the VREF pin to ground. Pulling the VREF pin low will also reset the logic and erase the volatile memory of the LM25066A. Once released, the VREF pin will charge up to its final value and the address will be latched into a volatile register once the voltage at the VREF exceeds 2.4 V.

8.5 Register Maps

8.5.1 PMBus Command Support

The device features an SMBus interface that allows the use of PMBus™ commands to set warn levels, error masks, and get telemetry on V_IN, V_OUT, I_IN, V_AUX, and P_IN. The supported PMBus™ commands are shown in Table 1.

Table 1. Supported PMBus™ Commands

CODE	NAME	FUNCTION	R/W	NUMBER OF DATA BYTES	DEFAULT VALUE
01h	OPERATION	Retrieves or stores the operation status	R/W	1	80h
03h	CLEAR_FAULTS	Clears the status registers and re-arms the black box registers for updating	Send Byte	0
19h	CAPABILITY	Retrieves the device capability	R	1	B0h
43h	VOUT_UV_WARN_LIMIT	Retrieves or stores output undervoltage warn limit threshold	R/W	2	0000h
4Fh	OT_FAULT_LIMIT	Retrieves or stores over-temperature fault limit threshold	R/W	2	0960h (150°C)
51h	OT_WARN_LIMIT	Retrieves or stores over-temperature warn limit threshold	R/W	2	07D0h (125°C)
57h	VIN_OV_WARN_LIMIT	Retrieves or stores input overvoltage warn limit threshold	R/W	2	0FFFh
58h	VIN_UV_WARN_LIMIT	Retrieves or stores input undervoltage warn limit threshold	R/W	2	0000h
78h	STATUS_BYTE	Retrieves information about the part operating status	R	1	49h
79h	STATUS_WORD	Retrieves information about the part operating status	R	2	3849h
7Ah	STATUS_VOUT	Retrieves information about output voltage status	R	1	00h
7Ch	STATUS_INPUT	Retrieves information about input status	R	1	10h
7Dh	STATUS_TEMPERATURE	Retrieves information about temperature status	R	1	00h
7Eh	STATUS_CML	Retrieves information about communications status	R	1	00h
80h	STATUS_MFR_SPECIFIC	Retrieves information about circuit breaker and MOSFET shorted status	R	1	10h
88h	READ_VIN	Retrieves input voltage measurement	R	2	0000h
8Bh	READ_VOUT	Retrieves output voltage measurement	R	2	0000h
8Dh	READ_TEMPERATURE_1	Retrieves temperature measurement	R	2	0190h
99h	MFR_ID	Retrieves manufacturer ID in ASCII characters (NSC)	R	3	4Eh 53h 43h
9Ah	MFR_MODEL	Retrieves part number in ASCII characters (LM25066A)	R	8	4Ch 4Dh 32h 35h 30h 36h 36h 0h
9Bh	MFR_REVISION	Retrieves part revision letter or number in ASCII (for example, AA)	R	2	41h 41h
D0h	MFR_SPECIFIC_00 READ_VAUX	Retrieves auxiliary voltage measurement	R	2	0000h
D1h	MFR_SPECIFIC_01 MFR_READ_IIN	Retrieves input current measurement	R	2	0000h
D2h	MFR_SPECIFIC_02 MFR_READ_PIN	Retrieves input power measurement	R	2	0000h
D3h	MFR_SPECIFIC_03 MFR_IIN_OC_WARN_LIMIT	Retrieves or stores input current limit warn threshold	R/W	2	0FFFh
D4h	MFR_SPECIFIC_04 MFR_PIN_OP_WARN_LIMIT	Retrieves or stores input power limit warn threshold	R/W	2	0FFFh
D5h	MFR_SPECIFIC_05 READ_PIN_PEAK	Retrieves measured maximum input power measurement	R	2	0000h
D6h	MFR_SPECIFIC_06 CLEAR_PIN_PEAK	Resets the contents of the peak input power register to zero	Send Byte	0
D7h	MFR_SPECIFIC_07 GATE_MASK	Disables external MOSFET gate control for FAULTs	R/W	1	0000h
D8h	MFR_SPECIFIC_08 ALERT_MASK	Retrieves or stores user SMBA fault mask	R/W	2	0820h
D9h	MFR_SPECIFIC_09 DEVICE_SETUP	Retrieves or stores information about number of retry attempts	R/W	1	0000h
DAh	MFR_SPECIFIC_10 BLOCK_READ	Retrieves most recent diagnostic and telemetry information in a single transaction	R	12	0460h 0000h 0000h 0000h 0000h 0000h
DBh	MFR_SPECIFIC_11 SAMPLES_FOR_AVG	Exponent value AVGN for number of samples to be averaged, range = 00h to 0Ch	R/W	1	00h
DCh	MFR_SPECIFIC_12 READ_AVG_VIN	Retrieves averaged input voltage measurement	R	2	0000h
DDh	MFR_SPECIFIC_13 READ_AVG_VOUT	Retrieves averaged output voltage measurement	R	2	0000h
DEh	MFR_SPECIFIC_14 READ_AVG_IIN	Retrieves averaged input current measurement	R	2	0000h
DFh	MFR_SPECIFIC_15 READ_AVG_PIN	Retrieves averaged input power measurement	R	2	0000h
E0h	MFR_SPECIFIC_16 BLACK_BOX_READ	Captures diagnostic and telemetry information which are latched when the first SMBA alert occurs after faults have been cleared	R	12	0000h 0000h 0000h 0000h 0000h 0000h
E1h	MFR_SPECIFIC_17 READ_DIAGNOSTIC_WORD	Manufacturer-specific parallel of the STATUS_WORD to convey all FAULT/WARN data in a single transaction	R	2	0460h
E2h	MFR_SPECIFIC_18 AVG_BLOCK_READ	Retrieves most recent average telemetry and diagnostic information in a single transaction	R	12	0460h 0000h 0000h 0000h 0000h 0000h

8.5.1.1 Standard PMBus™ Commands

8.5.1.1.1 OPERATION (01h)

The OPERATION command is a standard PMBus™ command that controls the MOSFET switch. This command may be used to switch the MOSFET ON and OFF under host control. It is also used to re-enable the MOSFET after a fault triggered shutdown. Writing an OFF command followed by an ON command will clear all faults. Writing only an ON command after a fault triggered shutdown will not clear the fault registers. The OPERATION command is issued with the write byte protocol.

Table 2. Recognized OPERATION Command Values

VALUE	MEANING	DEFAULT
80h	Switch ON	80h
00h	Switch OFF	–

8.5.1.1.2 CLEAR_FAULTS (03h)

The CLEAR_FAULTS command is a standard PMBus™ command that resets all stored warning and fault flags and the SMBA signal. If a fault or warning condition still exists when the CLEAR_FAULTS command is issued, the SMBA signal may not clear or will re-assert almost immediately. Issuing a CLEAR_FAULTS command will not cause the MOSFET to switch back on in the event of a fault turnoff: that must be done by issuing an OPERATION command after the fault condition is cleared. This command uses the PMBus™ send byte protocol.

8.5.1.1.3 CAPABILITY (19h)

The CAPABILITY command is a standard PMBus™ command that returns information about the PMBus™ functions supported by the LM25066A. This command is read with the PMBus™ read byte protocol.

Table 3. CAPABILITY Register

VALUE	MEANING	DEFAULT
B0h	Supports packet error check, 400 Kbits/sec, supports SMBus alert	B0h

8.5.1.1.4 VOUT_UV_WARN_LIMIT (43h)

The VOUT_UV_WARN_LIMIT command is a standard PMBus™ command that allows configuring or reading the threshold for the VOUT Undervoltage Warning detection. Reading and writing to this register should use the coefficients shown in Table 41. Accesses to this command should use the PMBus™ read or write word protocol. If the measured value of VOUT falls below the value in this register, VOUT UV Warn Limit flags are set in the respective registers, and the SMBA signal is asserted.

Table 4. VOUT_UV_WARN_LIMIT Register

VALUE	MEANING	DEFAULT
1h – 0FFFh	VOUT undervoltage warning detection threshold	0000h (disabled)
0000h	VOUT undervoltage warning disabled	–

8.5.1.1.5 OT_FAULT_LIMIT (4Fh)

The OT_FAULT_LIMIT is a standard PMBus™ command that allows configuring or reading the threshold for the Overtemperature Fault detection. Reading and writing to this register should use the coefficients shown in Table 41. Accesses to this command should use the PMBus™ read or write word protocol. If the measured temperature exceeds this value, an overtemperature fault is triggered, the MOSFET is switched off, OT Fault flags are set in the respective registers, and the SMBA signal is asserted. After the measured temperature falls below the value in this register, the MOSFET may be switched back on with the OPERATION command. A single temperature measurement is an average of 16 round-robin cycles. Therefore, the minimum temperature fault detection time is 16 ms.

Table 5. OT_FAULT_LIMIT Register

VALUE	MEANING	DEFAULT
0h – 0FFEh	Overtemperature fault threshold value	0960h (150°C)
0FFFh	Overtemperature fault detection disabled	–

8.5.1.1.6 OT_WARN_LIMIT (51h)

The OT_WARN_LIMIT is a standard PMBus™ command that allows configuring or reading the threshold for the Overtemperature Warning detection. Reading and writing to this register should use the coefficients shown in Table 41. Accesses to this command should use the PMBus™ read or write word protocol. If the measured temperature exceeds this value, an overtemperature warning is triggered, the OT Warn flags are set in the respective registers, and the SMBA signal is asserted. A single temperature measurement is an average of 16 round-robin cycles. Therefore, the minimum temperature warn detection time is 16 ms.

Table 6. OT_WARN_LIMIT Register

VALUE	MEANING	DEFAULT
0h – 0FFEh	Overtemperature warn threshold value	07D0h (125°C)
0FFFh	Overtemperature warn detection disabled	–

8.5.1.1.7 VIN_OV_WARN_LIMIT (57h)

The VIN_OV_WARN_LIMIT is a standard PMBus™ command that allows configuring or reading the threshold for the VIN Overvoltage Warning detection. Reading and writing to this register should use the coefficients shown in Table 41. Accesses to this command should use the PMBus™ read or write word protocol. If the measured value of VIN rises above the value in this register, VIN OV Warn flags are set in the respective registers, and the SMBA signal is asserted.

Table 7. VIN_OV_WARN_LIMIT Register

VALUE	MEANING	DEFAULT
0h – 0FFEh	VIN Overvoltage warning detection threshold	0FFFh (disabled)
0FFFh	VIN Overvoltage warning disabled	–

8.5.1.1.8 VIN_UV_WARN_LIMIT (58h)

The VIN_UV_WARN_LIMIT is a standard PMBus™ command that allows configuring or reading the threshold for the VIN Undervoltage Warning detection. Reading and writing to this register should use the coefficients shown in Table 41. Accesses to this command should use the PMBus™ read or write word protocol. If the measured value of VIN falls below the value in this register, VIN UV Warn flags are set in the respective registers, and the SMBA signal is asserted.

Table 8. VIN_UV_WARN_LIMIT Register

VALUE	MEANING	DEFAULT
1h – 0FFFh	VIN Undervoltage warning detection threshold	0000h (disabled)
0000h	VIN Undervoltage warning disabled	–

8.5.1.1.9 STATUS_BYTE (78h)

The STATUS_BYTE command is a standard PMBus™ command that returns the value of a number of flags indicating the state of the LM25066A. Accesses to this command should use the PMBus™ read byte protocol. To clear bits in this register, the underlying fault should be removed and a CLEAR_FAULTS command issued.

Table 9. STATUS_BYTE Definitions

BIT	NAME	MEANING	DEFAULT
7	BUSY	Not supported, always 0	0
6	OFF	This bit is asserted if the MOSFET is not switched on for any reason	1
5	VOUT OV	Not supported, always 0	0
4	IOUT OC	Not supported, always 0	0
3	VIN UV FAULT	A VIN undervoltage fault has occurred	1
2	TEMPERATURE	A temperature fault or warning has occurred	0
1	CML	A communication fault has occurred	0
0	None of the above	A fault or warning not listed in bits [7:1] has occurred	1

8.5.1.1.10 STATUS_WORD (79h)

The STATUS_WORD command is a standard PMBus™ command that returns the value of a number of flags indicating the state of the LM25066A. Accesses to this command should use the PMBus™ read word protocol. To clear bits in this register, the underlying fault should be removed and a CLEAR_FAULTS command issued. The INPUT and VIN UV FAULT flags will default to 1 on start-up. However, they will be cleared to 0 after the first time the input voltage exceeds the resistor programmed UVLO threshold.

Table 10. STATUS_WORD Definitions

BIT	NAME	MEANING	DEFAULT
15	VOUT	An output voltage fault or warning has occurred	0
14	IOUT/POUT	Not supported, always 0	0
13	INPUT	An input voltage or current fault has occurred	1
12	MFR	A manufacturer specific fault or warning has occurred	1
11	POWER GOOD	The Power Good signal has been negated	1
10	FANS	Not supported, always 0	0
9	OTHER	Not supported, always 0	0
8	UNKNOWN	Not supported, always 0	0
7	BUSY	Not supported, always 0	0
6	OFF	This bit is asserted if the MOSFET is not switched on for any reason	1
5	VOUT OV	Not supported, always 0	0
4	IOUT OC	Not supported, always 0	0
3	VIN UV FAULT	A VIN undervoltage fault has occurred	1
2	TEMPERATURE	A temperature fault or warning has occurred	0
1	CML	A communication fault has occurred	0
0	None of the above	A fault or warning not listed in bits [7:1] has occurred	1

8.5.1.1.11 STATUS_VOUT (7Ah)

The STATUS_VOUT command is a standard PMBus™ command that returns the value of the VOUT UV Warning flag. Accesses to this command should use the PMBus™ read byte protocol. To clear bits in this register, the underlying fault should be removed and a CLEAR_FAULTS command issued.

Table 11. STATUS_VOUT Definitions

BIT	NAME	MEANING
7	VOUT OV fault	Not supported, always 0
6	VOUT OV warn	Not supported, always 0
5	VOUT UV warn	A VOUT undervoltage warning has occurred
4	VOUT UV fault	Not supported, always 0
3	VOUT max	Not supported, always 0
2	TON max fault	Not supported, always 0
1	TOFF max fault	Not supported, always 0
0	VOUT tracking error	Not supported, always 0

8.5.1.1.12 STATUS_INPUT (7Ch)

The STATUS_INPUT command is a standard PMBus™ command that returns the value of a number of flags related to input voltage, current, and power. Accesses to this command should use the PMBus™ read byte protocol. To clear bits in this register, the underlying fault should be removed and a CLEAR_FAULTS command issued. The VIN UV Warn flag will default to 1 on start-up. However, it will be cleared to 0 after the first time the input voltage exceeds the resistor programmed UVLO threshold.

Table 12. STATUS_INPUT Definitions

BIT	NAME	MEANING	DEFAULT
7	VIN OV fault	A VIN overvoltage fault has occurred	0
6	VIN OV warn	A VIN overvoltage warning has occurred	0
5	VIN UV warn	A VIN undervoltage warning has occurred	1
4	VIN UV fault	A VIN undervoltage fault has occurred	0
3	Insufficient voltage	Not supported, always 0	0
2	IIN OC fault	An IIN overcurrent fault has occurred	0
1	IIN OC warn	An IIN overcurrent warning has occurred	0
0	PIN OP warn	A PIN over-power warning has occurred	0

8.5.1.1.13 STATUS_TEMPERATURE (7Dh)

The STATUS_TEMPERATURE is a standard PMBus™ command that returns the value of the of a number of flags related to the temperature telemetry value. Accesses to this command should use the PMBus™ read byte protocol. To clear bits in this register, the underlying fault should be removed and a CLEAR_FAULTS command issued.

Table 13. STATUS_TEMPERATURE Definitions

BIT	NAME	MEANING
7	Overtemp fault	An overtemperature fault has occurred
6	Overtemp warn	An overtemperature warning has occurred
5	Undertemp warn	Not supported, always 0
4	Undertemp fault	Not supported, always 0
3	Reserved	Not supported, always 0
2	Reserved	Not supported, always 0
1	Reserved	Not supported, always 0
0	Reserved	Not supported, always 0

8.5.1.1.14 STATUS_CML (7Eh)

The STATUS_CML command is a standard PMBus™ command that returns the value of a number of flags related to communication faults. Accesses to this command should use the PMBus™ read byte protocol. To clear bits in this register, a CLEAR_FAULTS command should be issued.

Table 14. STATUS_CML Definitions

BIT	NAME	DEFAULT
7	Invalid or unsupported command received	0
6	Invalid or unsupported data received	0
5	Packet error check failed	0
4	Memory fault detected not supported, always 0	0
3	Processor fault detected not supported, always 0	0
2	Reserved not supported, always 0	0
1	Miscellaneous communications fault has occurred	0
0	Other memory or logic fault detected not supported, always 0	0

8.5.1.1.15 STATUS_MFR_SPECIFIC (80h)

The STATUS_MFR_SPECIFIC command is a standard PMBus™ command that contains manufacturer specific status information. Accesses to this command should use the PMBus™ read byte protocol. To clear bits in this register, the underlying fault should be removed and a CLEAR_FAULTS command should be issued.

Table 15. STATUS_MFR_SPECIFIC Definitions

BIT	MEANING	DEFAULT
7	Circuit breaker fault	0
6	Ext. MOSFET shorted fault	0
5	Not supported, always 0	0
4	Defaults loaded	1
3	Not supported, always 0	0
2	Not supported, always 0	0
1	Not supported, always 0	0
0	Not supported, always 0	0

8.5.1.1.16 READ_VIN (88h)

The READ_VIN command is a standard PMBus™ command that returns the 12-bit measured value of the input voltage. Reading this register should use the coefficients shown in Table 41. Accesses to this command should use the PMBus™ read word protocol. This value is also used internally for the VIN Over and Under Voltage Warning detection.

Table 16. READ_VIN Register

VALUE	MEANING	DEFAULT
0h – 0FFFh	Measured value for VIN	0000h

8.5.1.1.17 READ_VOUT (8Bh)

The READ_VOUT command is a standard PMBus™ command that returns the 12-bit measured value of the output voltage. Reading this register should use the coefficients shown in Table 41. Accesses to this command should use the PMBus™ read word protocol. This value is also used internally for the VOUT Under Voltage Warning detection.

Table 17. READ_VOUT Register

VALUE	MEANING	DEFAULT
0h – 0FFFh	Measured value for VOUT	0000h

8.5.1.1.18 READ_TEMPERATURE_1 (8Dh)

The READ_TEMPERATURE _1 command is a standard PMBus™ command that returns the signed value of the temperature measured by the external temperature sense diode. Reading this register should use the coefficients shown in Table 41. Accesses to this command should use the PMBus™ read word protocol. This value is also used internally for the Over Temperature Fault and Warning detection. This data has a range of -256°C to + 255°C after the coefficients are applied.

Table 18. READ_TEMPERATURE_1 Register

VALUE	MEANING	DEFAULT
0h – 0FFFh	Measured value for TEMPERATURE	0000h

8.5.1.1.19 MFR_ID (99h)

The MFR_ID command is a standard PMBus™ command that returns the identification of the manufacturer. To read the MFR_ID, use the PMBus™ block read protocol.

Table 19. MFR_ID Register

BYTE	NAME	VALUE
0	Number of bytes	03h
1	MFR ID-1	4Eh ‘N'
2	MFR ID-2	53h ‘S'
3	MFR ID-3	43h ‘C'

8.5.1.1.20 MFR_MODEL (9Ah)

The MFR_MODEL command is a standard PMBus™ command that returns the part number of the chip. To read the MFR_MODEL, use the PMBus™ block read protocol.

Table 20. MFR_MODEL Register

BYTE	NAME	VALUE
0	Number of bytes	08h
1	MFR ID-1	4Ch ‘L'
2	MFR ID-2	4Dh ‘M'
3	MFR ID-3	32h ‘2'
4	MFR ID-4	35h ‘5'
5	MFR ID-5	30h ‘0'
6	MFR ID-6	36h ‘6'
7	MFR ID-7	36h ‘6'
8	MFR ID-8	00h

8.5.1.1.21 MFR_REVISION (9Bh)

The MFR_REVISION command is a standard PMBus™ command that returns the revision level of the part. To read the MFR_REVISION, use the PMBus™ block read protocol.

Table 21. MFR_REVISION Register

BYTE	NAME	VALUE
0	Number of bytes	02h
1	MFR ID-1	41h ‘A'
2	MFR ID-2	41h ‘A'

8.5.1.2 Manufacturer Specific PMBus™ Commands

8.5.1.2.1 MFR_SPECIFIC_00: READ_VAUX (D0h)

The READ_VAUX command will report the 12-bit ADC measured auxiliary voltage. Voltages greater than or equal to 1.16 V to ground will be reported at plus full scale (0FFFh). Voltages less than or equal to 0 V referenced to ground will be reported as 0 (0000h). Coefficients for the VAUX value are dependent on the value of the external divider (if used). To read data from the READ_VAUX command, use the PMBus™ Read Word protocol.

Table 22. READ_VAUX Register

VALUE	MEANING	DEFAULT
0h – 0FFFh	Measured value for VAUX input	0000h

8.5.1.2.2 MFR_SPECIFIC_01: MFR_READ_IIN (D1h)

The MFR_READ_IIN command will report the 12-bit ADC measured current sense voltage. To read data from the MFR_READ_IIN command, use the PMBus™ Read Word protocol. Reading this register should use the coefficients shown in Table 41. See Determining Telemetry Coefficients Empirically With Linear Fit to calculate the values to use.

Table 23. MFR_READ_IIN Register

VALUE	MEANING	DEFAULT
0h – 0FFFh	Measured value for input current sense voltage	0000h

8.5.1.2.3 MFR_SPECIFIC_02: MFR_READ_PIN (D2h)

The MFR_ READ_PIN command will report the upper 12 bits of the VIN × IIN product as measured by the 12-bit ADC. To read data from the MFR_READ_PIN command, use the PMBus™ Read Word protocol. Reading this register should use the coefficients shown in Table 41. Please see the section on coefficient calculations to calculate the values to use.

Table 24. MFR_READ_PIN Register

VALUE	MEANING	DEFAULT
0h – 0FFFh	Value for input current × input voltage	0000h

8.5.1.2.4 MFR_SPECIFIC_03: MFR_IN_OC_WARN_LIMIT (D3h)

The MFR_IIN_OC_ WARN_LIMIT PMBus™ command sets the input overcurrent warning threshold. In the event that the input current rises above the value set in this register, the IIN overcurrent flags are set in the status registers and the SMBA is asserted. To access the MFR_IIN_ OC_WARN_LIMIT register, use the PMBus™ Read/Write Word protocol. Reading/writing to this register should use the coefficients shown in Table 41.

Table 25. MFR_IIN_OC_WARN_LIMIT Register

VALUE	MEANING	DEFAULT
0h – 0FFEh	Value for input overcurrent warn limit	0FFFh
0FFFh	Input overcurrent warning disabled	–

8.5.1.2.5 MFR_SPECIFIC_04: MFR_PIN_OP_WARN_LIMIT (D4h)

The MFR_PIN_OP_WARN_LIMIT PMBus™ command sets the input over-power warning threshold. In the event that the input power rises above the value set in this register, the PIN Over-power flags are set in the status registers and the SMBA is asserted. To access the MFR_PIN_OP_WARN_LIMIT register, use the PMBus™ Read/Write Word protocol. Reading/writing to this register should use the coefficients shown in Table 41.

Table 26. MFR_PIN_OP_WARN_LIMIT Register

VALUE	MEANING	DEFAULT
0h – 0FFEh	Value for input over-power warn limit	0FFFh
0FFFh	Input over-power warning disabled	–

8.5.1.2.6 MFR_SPECIFIC_05: READ_PIN_PEAK (D5h)

The READ_PIN_PEAK command will report the maximum input power measured since a Power-On-Reset or the last CLEAR_PIN_PEAK command. To access the READ_PIN_PEAK command, use the PMBus™ Read Word protocol. Use the coefficients shown in Table 41.

Table 27. READ_PIN_PEAK Register

VALUE	MEANING	DEFAULT
0h – 0FFEh	Maximum value for input current × input voltage since reset or last clear	0h

8.5.1.2.7 MFR_SPECIFIC_06: CLEAR_PIN_PEAK (D6h)

The CLEAR_PIN_PEAK command will clear the PIN_PEAK register. This command uses the PMBus™ Send Byte protocol.

8.5.1.2.8 MFR_SPECIFIC_07: GATE_MASK (D7h)

The GATE_MASK register allows the hardware to prevent fault conditions from switching off the MOSFET. When the bit is high, the corresponding FAULT has no control over the MOSFET gate. All status registers will still be updated (STATUS, DIAGNOSTIC) and an SMBA will still be issued. This register is accessed with the PMBus™ Read / Write Byte protocol.

WARNING

Inhibiting the MOSFET switch off in response to overcurrent or circuit breaker fault conditions will likely result in the destruction of the MOSFET. This functionality should be used with great care and supervision.

Table 28. GATE_MASK Register

BIT	NAME	DEFAULT
7	Not used, always 0	0
6	Not used, always 0	0
5	VIN UV FAULT	0
4	VIN OV FAULT	0
3	Not used, do not write to bit	0
2	OVERTEMP FAULT	0
1	Not used, always 0	0
0	Not used, do not write to bit	0

8.5.1.2.9 MFR_SPECIFIC_08: ALERT_MASK (D8h)

The ALERT_MASK is used to mask the SMBA when a specific fault or warning has occurred. Each bit corresponds to one of the 14 different analog and digital faults or warnings that would normally result in an SMBA being set. When the corresponding bit is high, that condition will not cause the SMBA to be asserted. If that condition occurs, the registers where that condition is captured will still be updated (STATUS registers, DIAGNOSTIC_WORD) and the external MOSFET gate control will still be active (VIN_OV_FAULT, VIN_UV_FAULT, IIN/PFET_FAULT, CB_FAULT, OT_FAULT). This register is accessed with the PMBus™ Read / Write Word protocol. The VIN UNDERVOLTGE FAULT flag will default to 1 on start-up. However, it will be cleared to 0 after the first time the input voltage exceeds the resistor programmed UVLO threshold.

Table 29. ALERT_MASK Definitions

BIT	NAME	DEFAULT
15	VOUT UNDERVOLTAGE WARN	0
14	IIN LIMIT warn	0
13	VIN UNDERVOLTAGE WARN	0
12	VIN OVERVOLTAGE WARN	0
11	POWER GOOD	1
10	OVERTEMP WARN	0
9	Not used	0
8	OVERPOWER LIMIT WARN	0
7	Not used	0
6	EXT_MOSFET_SHORTED	0
5	VIN UNDERVOLTAGE FAULT	1
4	VIN OVERVOLTAGE FAULT	0
3	IIN/PFET FAULT	0
2	OVERTEMPERATURE FAULT	0
1	CML FAULT (communications fault)	0
0	CIRCUIT BREAKER FAULT	0

8.5.1.2.10 MFR_SPECIFIC_09: DEVICE_SETUP (D9h)

The DEVICE_SETUP command may be used to override pin settings to define operation of the LM25066A under host control. This command is accessed with the PMBus™ read / write byte protocol.

Table 30. DEVICE_SETUP Byte Format

BIT	NAME	MEANING
7:5	Retry setting	111 = Unlimited retries
		110 = Retry 16 times
		101 = Retry 8 times
		100 = Retry 4 times
		011 = Retry 2 times
		010 = Retry 1 time
		001 = No retries
		000 = Pin configured retries
4	Current limit setting	0 = Low setting (25 mV)
4	Current limit setting	1 = High setting (46 mV)
3	CB/CL ratio	0 = Low setting (1.8x)
3	CB/CL ratio	1 = High setting (3.6x)
2	Current limit configuration	0 = Use pin settings
2	Current limit configuration	1 = Use SMBus settings
1	Circuit breaker configuration	0 = Use pin settings
1	Circuit breaker configuration	1 = Use SMBus settings
0	Unused	–

In order to configure the Current Limit Setting via this register, it is necessary to set the Current Limit Configuration bit (2) to 1 to enable the register to control the current limit function and the Current Limit Setting bit (4) to select the desired setting. Similarly, in order to control the Circuit Breaker via this register, it is necessary to set the Circuit Breaker Configuration bit (1) to 1 to enable the register to control the Circuit Breaker Setting, and the Circuit Breaker / Current Limit Ratio bit (3) to the desired value. If the respective Configuration bits are not set, the Settings will be ignored and the pin set values used.

The Current Limit Configuration effects the coefficients used for the Current and Power measurements and warning registers.

8.5.1.2.11 MFR_SPECIFIC_10: BLOCK_READ (DAh)

The BLOCK_READ command concatenates the DIAGNOSTIC_WORD with input and output telemetry information (IIN, VOUT, VIN, PIN) as well as TEMPERATURE to capture all of the operating information of the LM25066A in a single SMBus transaction. The block is 12 bytes long with telemetry information being sent out in the same manner as if an individual READ_XXX command had been issued (shown below). The contents of the block read register are updated every clock cycle (85 ns) as long as the SMBus interface is idle. BLOCK_READ also guarantees that the VIN, VOUT, IIN and PIN measurements are all time-aligned whereas there is a chance they may not be if read with individual PMBus™ commands.

The Block Read command is read via the PMBus™ block read protocol.

Table 31. BLOCK_READ Register Format

BYTE COUNT (ALWAYS 12)	(1 BYTE)
DIAGNOSTIC_WORD	(1 word)
IIN_BLOCK	(1 word)
VOUT_BLOCK	(1 word)
VIN_BLOCK	(1 word)
PIN_BLOCK	(1 word)
TEMP_BLOCK	(1 word)

8.5.1.2.12 MFR_SPECIFIC_11: SAMPLES_FOR_AVG (DBh)

The SAMPLES_FOR_AVERAGE is a manufacturer specific command for setting the number of samples used in computing the average values for IIN, VIN, VOUT, PIN. The decimal equivalent of the AVGN nibble is the power of 2 samples (for example, AVGN=12 equates to 4096 samples used in computing the average). The LM25066A supports average numbers of 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096. The SAMPLES_FOR_AVG number applies to average values of IIN, VIN, VOUT, PIN simultaneously. The LM25066A uses simple averaging. This is accomplished by summing consecutive results up to the number programmed, then dividing by the number of samples. Averaging is calculated according to the following sequence:

Equation 1. Y = (X_(N) + X_(N-1) + ... + X₍₀₎) / 2^AVGN

When the averaging has reached the end of a sequence (for example, 4096 samples are averaged), then a whole new sequence begins that will require the same number of samples (in this example, 4096) to be taken before the new average is ready.

Table 32. SAMPLES_FOR_AVG Register

AVGN	N=2^N AVERAGES	AVERAGING/REGISTER UPDATE PERIOD (ms)
0000	1	1
0001	2	2
0010	4	4
0011	8	8
0100	16	16
0101	32	32
0110	64	64
0111	128	128
1000	256	256
1001	512	512
1010	1024	1024
1011	2048	2048
1100	4096	4096

Note that a change in the SAMPLES_FOR_AVG register will not be reflected in the average telemetry measurements until the present averaging interval has completed. The default setting for AVGN is 0000 and therefore the average telemetry will mirror the instantaneous telemetry until a value higher than zero is programmed.

The SAMPLES_FOR_AVG register is accessed via the PMBus™ read / write byte protocol.

Table 33. SAMPLES_FOR_AVG Register

VALUE	MEANING	DEFAULT
0h – 0Ch	Exponent (AVGN) for number of samples to average over	00h

8.5.1.2.13 MFR_SPECIFIC_12: READ_AVG_VIN (DCh)

The READ_AVG_VIN command will report the 12-bit ADC measured input average voltage. If the data is not ready, the returned value will be the previous averaged data. However, if there is no previously averaged data, the default value (0000h) will be returned. This data is read with the PMBus™ Read Word protocol. This register should use the coefficients shown in Table 41.

Table 34. READ_AVG_VIN Register

VALUE	MEANING	DEFAULT
0h – 0FFFh	Average of measured values for input voltage	0000h

8.5.1.2.14 MFR_SPECIFIC_13: READ_AVG_VOUT (DDh)

The READ_AVG_VOUT command will report the 12-bit ADC measured average output voltage. The returned value will be the default value (0000h) or previous data when the average data is not ready. This data is read with the PMBus™ Read Word protocol. This register should use the coefficients shown in Table 41.

Table 35. READ_AVG_VOUT Register

VALUE	MEANING	DEFAULT
0h – 0FFFh	Average of measured values for output voltage	0000h

8.5.1.2.15 MFR_SPECIFIC_14: READ_AVG_IIN (DEh)

The READ AVG_IIN command will report the 12-bit ADC measured current sense average voltage. The returned value will be the default value (0000h) or previous data when the average data is not ready. This data is read with the PMBus™ Read Word protocol. This register should use the coefficients shown in Table 41.

Table 36. READ_AVG_IIN Register

VALUE	MEANING	DEFAULT
0h – 0FFFh	Average of measured values for current sense voltage	0000h

8.5.1.2.16 MFR_SPECIFIC_15: READ_AVG_PIN (DFh)

The READ_AVG_PIN command will report the upper 12 bits of the average VIN × IIN product as measured by the 12-bit ADC. You will read the default value (0000h) or previous data when the average data is not ready. This data is read with the PMBus™ Read Word protocol. This register should use the coefficients shown in Table 41.

Table 37. READ_AVG_PIN Register

VALUE	MEANING	DEFAULT
0h – 0FFFh	Average of measured value for input voltage × input current sense voltage	0000h

8.5.1.2.17 MFR_SPECIFIC_16: BLACK_BOX_READ (E0h)

The BLACK_BOX_READ command retrieves the BLOCK_READ data which was latched in at the first assertion of SMBA. It is re-armed with the CLEAR_FAULTS command. It is the same format as the BLOCK_READ registers, the only difference being that its contents are updated with the SMBA edge rather than the internal clock edge. This command is read with the PMBus™ Block Read protocol.

8.5.1.2.18 MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h)

The READ_DIAGNOSTIC_WORD PMBus command will report all of the LM25066A faults and warnings in a single read operation. The standard response to the assertion of the SMBA signal of issuing multiple read requests to various status registers can be replaced by a single word read to the DIAGNOSTIC_WORD register. The READ_DIAGNOSTIC_WORD command should be read with the PMBus™ Read Word protocol. The DIAGNOSTIC_WORD is also returned in the BLOCK_READ, BLACK_BOX_READ, and AVG_BLOCK_READ operations.

Table 38. READ_DIAGNOSTIC_WORD Format

BIT	MEANING	DEFAULT
15	VOUT_UNDERVOLTAGE_WARN	0
14	IIN_OP_WARN	0
13	VIN_UNDERVOLTAGE_WARN	0
12	VIN_OVERVOLTAGE_WARN	0
11	POWER GOOD	1
10	OVER_TEMPERATURE_WARN	0
9	TIMER_LATCHED_OFF	0
8	EXT_MOSFET_SHORTED	0
7	CONFIG_PRESET	1
6	DEVICE_OFF	1
5	VIN_UNDERVOLTAGE_FAULT	1
4	VIN_OVERVOLTAGE_FAULT	0
3	IIN_OC/PFET_OP_FAULT	0
2	OVER_TEMPERATURE_FAULT	0
1	CML_FAULT	0
0	CIRCUIT_BREAKER_FAULT	0

8.5.1.2.19 MFR_SPECIFIC_18: AVG_BLOCK_READ (E2h)

The AVG_BLOCK_READ command concatenates the DIAGNOSTIC_WORD with input and output average telemetry information (IIN, VOUT, VIN, PIN) as well as TEMPERATURE to capture all of the operating information of the part in a single PMBus™ transaction. The block is 12 bytes long with telemetry information being sent out in the same manner as if an individual READ_AVG_XXX command had been issued (shown below). AVG_BLOCK_READ also guarantees that the VIN, VOUT, PIN, and IIN measurements are all time-aligned whereas there is a chance they may not be if read with individual PMBus™ commands. To read data from the AVG_BLOCK_READ command, use the SMBus Block Read protocol.

Table 39. AVG_BLOCK_READ Register Format

BYTE COUNT (ALWAYS 12)	(1 BYTE)
DIAGNOSTIC_WORD	(1 word)
AVG_IIN	(1 word)
AVG_VOUT	(1 word)
AVG_VIN	(1 word)
AVG_PIN	(1 word)
TEMPERATURE	(1 word)

Figure 36. Command / Register and Alert Flow Diagram

8.5.1.3 Reading and Writing Telemetry Data and Warning Thresholds

All telemetry data is measured using a 12-bit ADC. This telemetry data and user programmed warning thresholds are communicated in 16-bit, two's compliment, signed data. This data is read or written in 2-byte increments conforming to the DIRECT format as described in section 8.3.3 of the PMBus™ Power System Management Protocol Specification 1.1 (Part II). The organization of the bits in the telemetry or warning word is shown in Table 40, where Bit_11 is the most significant bit (MSB) and Bit_0 is the least significant bit (LSB). The decimal equivalent of all warning and telemetry words are constrained to be within the range of 0 to 4095, with the exception of temperature. The decimal equivalent value of the temperature word ranges from 0 to 65535.

Table 40. Telemetry and Warning Word Format

BYTE	B7	B6	B5	B4	B3	B2	B1	B0
1	Bit_7	Bit_6	Bit_5	Bit_4	Bit_3	Bit_2	Bit_1	Bit_0
2	0	0	0	0	Bit_11	Bit_10	Bit_9	Bit_8

Conversion from direct format to real world dimensions of current, voltage, power, and temperature is accomplished by determining appropriate coefficients as described in section 7.2.1 of the PMBus™ Power System Management Protocol Specification 1.1 (Part II). According to this specification, the host system converts the values received into a reading of volts, amperes, watts, or other units using Equation 2:

Equation 2. LM25066A 30115803.gif

where

X: the calculated "real world" value (volts, amps, watt, and so forth)
M: the slope coefficient
Y: a two byte two's complement integer received from device
B: the offset, a two byte two's complement integer
R: the exponent, a one byte two's complement integer
R is only necessary in systems where m is required to be an integer (for example, where m may be stored in a register in an integrated circuit). In those cases, R only needs to be large enough to yield the desired accuracy.

Table 41. Telemetry and Warning Conversion Coefficients (R_S in mΩ)

COMMANDS	CONDITION	FORMAT	NUMBER OF DATA BYTES	M	B	R	UNIT
READ_VIN, READ_AVG_VIN VIN_OV_WARN_LIMIT VIN_UV_WARN_LIMIT		DIRECT	2	22070	–1800	–2	V
READ_VOUT, READ_AVG_VOUT VOUT_UV_WARN_LIMIT		DIRECT	2	22070	–1800	–2	V
READ_VAUX		DIRECT	2	3546	–3	0	V
*READ_IIN, READ_AVG_IIN MFR_IIN_OC_WARN_LIMIT	CL = GND	DIRECT	2	13661 × R_S	–5200	–2	A
*READ_IIN, READ_AVG_IIN MFR_IIN_OC_WARN_LIMIT	CL = VDD	DIRECT	2	6854 × R_S	–3100	–2	A
*READ_PIN, READ_AVG_PIN, READ_PIN_PEAK MFR_PIN_OP_WARN_LIMIT	CL = GND	DIRECT	2	736 × R_S	–3300	–2	W
*READ_PIN, READ_AVG_PIN, READ_PIN_PEAK MFR_PIN_OP_WARN_LIMIT	CL = VDD	DIRECT	2	369 × R_S	–1900	–2	W
READ_TEMPERATURE_1 OT_WARN_LIMIT OT_FAULT_LIMIT		DIRECT	2	16000	0	–3	°C

Care must be taken to adjust the exponent coefficient, R, such that the value of m remains within the range of
–32768 to 32767. For example, if a 5-mΩ sense resistor is used, the correct coefficients for the READ_IIN command with CL = VDD would be m = 6830, b = –310, R = –1.

8.5.1.4 Determining Telemetry Coefficients Empirically With Linear Fit

The coefficients for telemetry measurements and warning thresholds presented in Table 41 are adequate for the majority of applications. Current and power coefficients must be calculated per application as they are dependent on the value of the sense resistor, RS, used. These were obtained by characterizing multiple units over temperature and are considered optimal. The small-signal nature of the current measurement make both current and power measurement more susceptible to PCB parasitics than other telemetry channels. In addition there is some variation in RS and the LM25066A itself. This may cause slight variations in the optimum coefficients (m, b, R) for converting from Direct Format digital values to real-world values (for example, amps and watts). To maximize telemetry accuracy, the coefficients can be calibrated for a given board using empirical methods. This would determine optimum coefficients to cancel out the error from PCB parasitics, RS variation, and the variation of the LM25066A. It is not considered good practice to take measurements on one board and use the computed coefficients for all units in production, because the RS and the LM25066A on a given board are randomly chosen and do not represent a statistical mean. It is recommended to either calibrate all boards individually or to use the recommended coefficients from Table 41.

The optimal current coefficients for a specific board can be determined using the following method:

While the LM25066A is in normal operation, measure the voltage across the sense resistor using kelvin test points and a high accuracy DVM while controlling the load current. Record the integer value returned by the READ_AVG_IIN command (with the SAMPLES_FOR_AVG set to a value greater than 0) for two or more voltages across the sense resistor. For best results, the individual READ_AVG_IIN measurements should span nearly the full scale range of the current (for example, voltage across R_S of 5 mV and 20 mV).
Convert the measured voltages to currents by dividing them by the value of R_S. For best accuracy, the value of R_S should be measured. Table 42 assumes a sense resistor value of 5 mΩ.

Table 42. Measurements for Linear Fit Determination of Current Coefficients

MEASURED VOLTAGE ACROSS R_S (V)	MEASURED CURRENT (A)	READ_AVG_IIN (INTERGER VALUE)
0.005	1	648
0.01	2	1331
0.02	4	2698

Using the spreadsheet or math program of your choice, determine the slope and the y-intercept values returned by the READ_AVG_IIN command versus the measured current. For the data shown in Table 42:
- READ_AVG_IIN value = slope × (Measured Current) + (y-intercept)
- slope = 683.4
- y-intercept = -35.5
To determine the M coefficient, simply shift the decimal point of the calculated slope to arrive at an integer with a suitable number of significant digits for accuracy (typically 4) while staying with the range of -32768 to +32767. This shift in the decimal point equates to the R coefficient. For the slope value shown above, the decimal point would be shifted to the right once hence R = –1.
Once the R coefficient has been determined, the B coefficient is found by multiplying the y-intercept by 10^-R. In this case the value of B = –355.

Calculated Current Coefficients:

M = 6834
B = -355
R = -1

Equation 3. LM25066A 30115803.gif

where

X: the calculated real world value (volts, amps, watts, temperature)
M: the slope coefficient, a the two byte two's complement integer
Y: a two byte, two's complement integer received from device
B: the offset, a two byte two's complement integer
R: the exponent, a one byte two's complement integer
The above procedure can be repeated to determine the coefficients of any telemetry channel simply by substituting measured current for some other parameter (for example, power, voltage, and so forth).

8.5.1.5 Writing Telemetry Data

There are several locations that will require writing data if their optional usage is desired. Use the same coefficients previously calculated for your application and apply them using this method as prescribed by the PMBus Power System Management Protocol Specification Part II – Command Language Revision 1.2, section 7.2.2.

Equation 4. Y = (mX + b) × 10^R

where

X: the calculated real world value (volts, amps, watts, temperature)
M: the slope coefficient, a two byte two's complement integer
Y: a two byte two's complement integer received from device
B: the offset, a two byte two's complement integer
R: the exponent, a one byte two's complement integer

8.5.1.6 PMBus™ Address Lines (ADR0, ADR1, ADR2)

The three address lines are to be set high (connect to VDD), low (connect to GND), or open to select one of 27 addresses for communicating with the LM25066A. Table 43 depicts 7-bit addresses (eighth bit is read/write bit).

Table 43. Device Addressing

ADR2	ADR1	ADR0	DECODED ADDRESS
Z	Z	Z	40h
Z	Z	0	41h
Z	Z	1	42h
Z	0	Z	43h
Z	0	0	44h
Z	0	1	45h
Z	1	Z	46h
Z	1	0	47h
Z	1	1	10h
0	Z	Z	11h
0	Z	0	12h
0	Z	1	13h
0	0	Z	14h
0	0	0	15h
0	0	1	16h
0	1	Z	17h
0	1	0	50h
0	1	1	51h
1	Z	Z	52h
1	Z	0	53h
1	Z	1	54h
1	0	Z	55h
1	0	0	56h
1	0	1	57h
1	1	Z	58h
1	1	0	59h
1	1	1	5Ah

8.5.1.7 SMBA Response

The SMBA effectively has two masks:

1. The Alert Mask Register at D8h, and

2. The ARA Automatic Mask.

The ARA Automatic Mask is a mask that is set in response to a successful ARA read. An ARA read operation returns the PMBus™ address of the lowest addressed part on the bus that has its SMBA asserted. A successful ARA read means that THIS part was the one that returned its address. When a part responds to the ARA read, it releases the SMBA signal. When the last part on the bus that has an SMBA set has successfully reported its address, the SMBA signal will de-assert.

The way that the LM25066A releases the SMBA signal is by setting the ARA Automatic mask bit for all fault conditions present at the time of the ARA read. All status registers will still show the fault condition, but it will not generate an SMBA on that fault again until the ARA Automatic mask is cleared by the host issuing a Clear Fault command to this part. This should be done as a routine part of servicing an SMBA condition on a part, even if the ARA read is not done. Figure 37 depicts a schematic version of this flow.

Figure 37. Typical Flow Schematic for SMBA Fault

ADR2	ADR1	ADR0	DECODED ADDRESS
Z	Z	Z	40h
Z	Z	0	41h
Z	Z	1	42h
Z	0	Z	43h
Z	0	0	44h
Z	0	1	45h
Z	1	Z	46h
Z	1	0	47h
Z	1	1	10h
0	Z	Z	11h
0	Z	0	12h
0	Z	1	13h
0	0	Z	14h
0	0	0	15h
0	0	1	16h
0	1	Z	17h
0	1	0	50h
0	1	1	51h
1	Z	Z	52h
1	Z	0	53h
1	Z	1	54h
1	0	Z	55h
1	0	0	56h
1	0	1	57h
1	1	Z	58h
1	1	0	59h
1	1	1	5Ah

ADR2	ADR1	ADR0	DECODED ADDRESS
Z	Z	Z	40h
Z	Z	0	41h
Z	Z	1	42h
Z	0	Z	43h
Z	0	0	44h
Z	0	1	45h
Z	1	Z	46h
Z	1	0	47h
Z	1	1	10h
0	Z	Z	11h
0	Z	0	12h
0	Z	1	13h
0	0	Z	14h
0	0	0	15h
0	0	1	16h
0	1	Z	17h
0	1	0	50h
0	1	1	51h
1	Z	Z	52h
1	Z	0	53h
1	Z	1	54h
1	0	Z	55h
1	0	0	56h
1	0	1	57h
1	1	Z	58h
1	1	0	59h
1	1	1	5Ah

ADR2	ADR1	ADR0	DECODED ADDRESS
Z	Z	Z	40h
Z	Z	0	41h
Z	Z	1	42h
Z	0	Z	43h
Z	0	0	44h
Z	0	1	45h
Z	1	Z	46h
Z	1	0	47h
Z	1	1	10h
0	Z	Z	11h
0	Z	0	12h
0	Z	1	13h
0	0	Z	14h
0	0	0	15h
0	0	1	16h
0	1	Z	17h
0	1	0	50h
0	1	1	51h
1	Z	Z	52h
1	Z	0	53h
1	Z	1	54h
1	0	Z	55h
1	0	0	56h
1	0	1	57h
1	1	Z	58h
1	1	0	59h
1	1	1	5Ah