SNVS572E July 2008 – January 2016 LM25037 , LM25037-Q1
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)(2)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VIN to GND | –0.3 | 76 | V | |
| VCC, RAMP , OUTA, OUTB to GND | –0.3 | 16 | V | |
| CS to GND | –0.3 | 1 | V | |
| UVLO, FB, RT2, RT1, SS, REF to GND | –0.3 | 7 | V | |
| COMP, RES(3) | ||||
| Junction temperature | 150 | °C | ||
| Storage temperature | –65 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications.
(3) COMP, RES are output pins. As such, TI does not recommend connecting external power sources to these pins.
6.2 ESD Ratings: LM25037
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±750 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings: LM25037-Q1
| VALUE | UNIT | ||||
|---|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±2000 | V | |
| Charged-device model (CDM), per AEC Q100-011 | All pins | ±750 | |||
| Corner pins (1, 8, 9, 16) | ±750 | ||||
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.4 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| VIN voltage | 5.5 | 75 | V | ||
| External voltage applied to VCC | 8 | 14 | V | ||
| Operating junction temperature | −40 | 125 | °C | ||
6.5 Thermal Information
| THERMAL METRIC(1) | LM25037/LM25037-Q1 | UNIT | |
|---|---|---|---|
| PW (TSSOP) | |||
| 16 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 99.9 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 32.6 | °C/W |
| RθJB | Junction-to-board thermal resistance | 45.8 | °C/W |
| ψJT | Junction-to-top characterization parameter | 2 | °C/W |
| ψJB | Junction-to-board characterization parameter | 45.1 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.6 Electrical Characteristics
VVIN = 12V, VVCC = 10V, RRT1 = 30.1 kΩ, RRT2 = 30.1 kΩ, VUVLO = 3 V, TJ =−40°C to +125° unless otherwise stated.(1)(2)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| START-UP REGULATOR (VCC PIN) | |||||||
| VVCC | VCC voltage | IVCC = 10 mA | 7.2 | 7.7 | 8.1 | V | |
| IVCC(Lim) | VCC current limit | VVCC = 7 V | 20 | mA | |||
| VVCC(UV) | VCC Undervoltage threshold | 4.6 | 5 | 5.4 | V | ||
| Hysteresis | 0.5 | V | |||||
| IVIN | Start-up regulator current | VVIN = 20 V, VUVLO = 0 V | 35 | 58 | µA | ||
| VVIN = 75 V, VUVLO = 0 V | 45 | 80 | µA | ||||
| Supply current into VCC from external source | Outputs and COMP open, VVCC = 10 V, Outputs switching | 4 | mA | ||||
| VOLTAGE REFERENCE REGULATOR (REF PIN) | |||||||
| VREF | REF Voltage | IREF = 0 mA | 4.75 | 5 | 5.15 | V | |
| REF Voltage Regulation | IREF = 0 to 2.5 mA | 7 | 25 | mV | |||
| IREF(Lim) | REF Current Limit | VREF = 4.5 V | 5 | 10 | mA | ||
| VREF Undervoltage threshold | 3.7 | 4 | 4.3 | V | |||
| VREF(UV) | Hysteresis | 0.4 | V | ||||
| UNDERVOLTAGE LOCKOUT AND SHUTDOWN (UVLO PIN) | |||||||
| VUVLO | Undervoltage threshold | 1.20 | 1.25 | 1.295 | V | ||
| IUVLO | Hysteresis current | UVLO pin sinking | 17 | 22 | 26 | µA | |
| Undervoltage shutdown threshold | UVLO voltage rising | 0.35 | 0.45 | 0.6 | V | ||
| Hysteresis | 0.1 | V | |||||
| CURRENT SENSE INPUT (CS PIN) | |||||||
| VCS | Current limit threshold | 0.22 | 0.255 | 0.29 | V | ||
| CS delay to output | CS from 0 V to 1 V. Time for OUTA and OUTB to fall to 90% of VCC. Output load = 0 pF. | 27 | ns | ||||
| Leading edge blanking time at CS | 65 | ns | |||||
| CS sink impedance (clocked) | Internal FET sink impedance | 21 | 45 | Ω | |||
| CURRENT LIMIT RESTART (RES PIN) | |||||||
| VRES | RES threshold | 1.9 | 2 | 2.2 | V | ||
| Charge source current | VRES = 1.5 V | 14 | 18 | 21 | µA | ||
| Discharge sink current | VRES = 1 V | 5 | 8 | 11 | µA | ||
| SOFT-START (SS PIN) | |||||||
| ISS | Charging current in normal operation | VSS = 0 | 70 | 100 | 130 | µA | |
| Charging current during a hiccup mode restart | VSS = 0 | 0.6 | 1 | 1.4 | µA | ||
| Soft-stop current sink | VSS = 2 V | 70 | 100 | 130 | µA | ||
| OSCILLATOR (RT1 AND RT2 PINS) | |||||||
| DT1 | Dead-time 1 | RRT2 = 15 kΩ | 40 | 75 | 105 | ns | |
| DT2 | Dead-time 2 | RRT2 = 50 kΩ | 250 | ns | |||
| FSW1 | Frequency 1 (at OUTA, half oscillator frequency) | RRT1 = 30.1 kΩ, RRT2 = 30.1 kΩ, | 178 | 200 | 222 | kHz | |
| FSW2 | Frequency 2 (at OUTA, half oscillator frequency) | RRT1 = 11 kΩ, RRT2 = 30.1 kΩ, | 448 | 515 | 578 | kHz | |
| DC level | 2 | V | |||||
| Input sync threshold | 2.5 | 3 | 3.4 | V | |||
| PWM CONTROLLER (COMP PIN) | |||||||
| Delay to output | 65 | ns | |||||
| VPWM-OS | SS to RAMP offset | 0.7 | 1 | 1.2 | V | ||
| Minimum duty cycle | VSS = 0 V | TJ = 25°C | 0% | ||||
| COMP open-circuit voltage | VFB = 0 V | 4.5 | 4.75 | 5 | V | ||
| COMP short-circuit current | VFB = 0 V, COMP = 0 V | 0.5 | 1 | 1.5 | mA | ||
| VOLTAGE FEED-FORWARD (RAMP PIN) | |||||||
| RAMP sink impedance (clocked) | 5 | 20 | Ω | ||||
| ERROR AMPLIFIER | |||||||
| GBW | Gain bandwidth | 4 | MHz | ||||
| DC gain | 75 | dB | |||||
| Input voltage | VFB = COMP | 1.22 | 1.245 | 1.27 | V | ||
| COMP sink capability | VFB = 1.5 V COMP = 1 V | TJ = 25°C | 5 | 13 | mA | ||
| FB bias current | 10 | nA | |||||
| MAIN OUTPUT DRIVERS (OUTA and OUTB Pins) | |||||||
| Output high voltage | IOUT = 50 mA, (source) | Vcc-0.5 | Vcc-0.25 | V | |||
| Output low voltage | IOUT = 100 mA (sink) | 0.2 | 0.5 | V | |||
| Rise time | CLOAD = 1 nF | 17 | ns | ||||
| Fall time | CLOAD = 1 nF | 18 | ns | ||||
| Peak source current | VVCC = 10 V | 1.2 | A | ||||
| Peak sink current | VVCC = 10 V | 1.2 | A | ||||
| THERMAL SHUTDOWN | |||||||
| TSD | Thermal shutdown threshold | 165 | °C | ||||
| Thermal shutdown hysteresis | 25 | °C | |||||
(1) All limits are ensured. All electrical characteristics having room temperature limits are tested during production at TA = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
(2) Typical specifications represent the most likely parametric norm at 25°C operation.
6.7 Typical Characteristics
