7.3.1 Precision Enable and UVLO

The precision enable input (EN) is used to control the regulator. The precision feature allows simple sequencing of multiple power supplies with a resistor divider from another supply. Connecting this pin to ground or to a voltage less than 1.6 V (typ) will turn off the regulator. The current drain from the input supply, in this state, is 25 µA (typ) at an input voltage of 12 V. The EN input has an internal pullup of about 6 µA. Therefore this pin can be left floating or pulled to a voltage greater than 2.2 V (typ) to turn the regulator on. The hysteresis on this input is about 0.6 V (typ) above the 1.6-V (typ) threshold. When driving the enable input, the voltage must never exceed the 6 V absolute maximum specification for this pin.

Although an internal pullup is provided on the EN pin, it is good practice to pull the input high, when this feature is not used, especially in noisy environments. This can most easily be done by connecting a resistor between VIN and the EN pin. The resistor is required, because the internal zener diode, at the EN pin, will conduct for voltages above about 6 V. The current in this zener must be limited to less than 100 µA. A resistor of 470 kΩ will limit the current to a safe value for input voltages as high 42 V. Smaller values of resistor can be used at lower input voltages.

The LM22672 device also incorporates an input undervoltage lock-out (UVLO) feature. This prevents the regulator from turning on when the input voltage is not great enough to properly bias the internal circuitry. The rising threshold is 4.3 V (typ) while the falling threshold is 3.9 V (typ). In some cases these thresholds may be too low to provide good system performance. The solution is to use the EN input as an external UVLO to disable the part when the input voltage falls below a lower boundary. This is often used to prevent excessive battery discharge or early turn-on during start-up. This method is also recommended to prevent abnormal device operation in applications where the input voltage falls below the minimum of 4.5 V. Figure 12 shows the connections to implement this method of UVLO. Equation 1 and Equation 2 can be used to determine the correct resistor values.

Equation 1.

Equation 2.

Where:

V_off is the input voltage where the regulator shuts off.

V_on is the voltage where the regulator turns on.

Due to the 6 µA pullup, the current in the divider should be much larger than this. A value of 20 kΩ, for R_ENB is a good first choice. Also, a zener diode may be needed between the EN pin and ground in order to comply with the absolute maximum ratings on this pin.

Figure 12. External UVLO Connections

7.3.2 Soft-Start

The soft-start feature allows the regulator to gradually reach steady-state operation, thus reducing start-up stresses. The internal soft-start feature brings the output voltage up in about 500 µs. This time can be extended by using an external capacitor connected to the SS pin. Values in the range of 100 nF to 1 µF are recommended. The approximate soft-start time can be estimated from Equation 3.

Equation 3.

Soft-start is reset any time the part is shut down or a thermal overload event occurs.

7.3.3 Switching Frequency Adjustment and Synchronization

The LM22672 device will operate in three different modes, depending on the condition of the RT/SYNC pin. With the RT/SYNC pin floating, the regulator will switch at the internally set frequency of 500 kHz (typ). With a resistor in the range of 25 kΩ to 200 kΩ, connected from RT/SYNC to ground, the internal switching frequency can be adjusted from 1 MHz to 200 kHz. Figure 13 shows the typical curve for switching frequency versus the external resistance connected to the RT/SYNC pin. The accuracy of the switching frequency, in this mode, is slightly worse than that of the internal oscillator; about ±25% is to be expected. Finally, an external clock can be applied to the RT/SYNC pin to allow the regulator to synchronize to a system clock or another LM22672. The mode is set during start up of the regulator. When the LM22672 is enabled, or after V_IN is applied, a weak pullup is connected to the RT/SYNC pin and, after approximately 100 µs, the voltage on the pin is checked against a threshold of about 0.8 V. With the RT/SYNC pin open, the voltage floats above this threshold, and the mode is set to run with the internal clock. With a frequency set resistor present, an internal reference holds the pin voltage at 0.8 V; thus, the resulting current sets the mode to allow the resistor to control the clock frequency. If the external circuit forces the RT/SYNC pin to a voltage much greater or less than 0.8 V, the mode is set to allow external synchronization. The mode is latched until either the EN or the input supply is cycled.

The choice of switching frequency is governed by several considerations. As an example, lower frequencies may be desirable to reduce switching losses or improve duty cycle limits. Higher frequencies, or a specific frequency, may be desirable to avoid problems with EMI or reduce the physical size of external components. The flexibility of increasing the switching frequency above 500 kHz can also be used to operate outside a critical signal frequency band for a given application. Keep in mind that the values of inductor and output capacitor cannot be reduced dramatically by operating above 500 kHz. This is true because the design of the internal loop compensation restricts the range of these components.

Frequency synchronization requires some care. First the external clock frequency must be greater than the internal clock frequency, and less than 1 MHz. The maximum internal switching frequency is ensured in the Electrical Characteristics table.

The synchronizing frequency must always be greater than the internal clock frequency. Secondly, the RT/SYNC pin must see a valid high or low voltage, during start-up, in order for the regulator to go into the synchronizing mode. Also, the amplitude of the synchronizing pulses must comport with V_SYNC levels found in the Electrical Characteristics table. The regulator will synchronize on the rising edge of the external clock. If the external clock is lost during normal operation, the regulator will revert to the 500 kHz (typ) internal clock.

If the frequency synchronization feature is used, current limit foldback is not operational; see the Current Limit section for details.

Figure 13. Switching Frequency vs RT/SYNC Resistor

7.3.4 Self-Synchronization

It is possible to synchronize multiple LM22672 regulators together to share the same switching frequency. This can be done by tying the RT/SYNC pins together through a MOSFET and connecting a 1 kΩ resistor to ground at each pin. Figure 14 shows this connection. The gate of the MOSFET should be connected to the regulator with the highest output voltage. Also, the EN pins of both regulators should be tied to the common system enable, in order to properly initialize both regulators. The operation is as follows: When the regulators are enabled, the outputs are low and the MOSFET is off. The 1 kΩ resistors pull the RT/SYNC pins low, thus enabling the synchronization mode. These resistors are small enough to pull the RT/SYNC pin low, rather than activate the frequency adjust mode. Once the output voltage of one of the regulators is sufficient to turn on the MOSFET, the two RT/SYNC pins are tied together and the regulators will run in synchronized mode. The two regulators will be clocked at the same frequency but slightly phase shifted according to the minimum off-time of the regulator with the fastest internal oscillator. The slight phase shift helps to reduce stress on the input capacitors of the regulator. It is important to choose a MOSFET with a low gate threshold voltage so that the MOSFET will be fully enhanced. Also, a MOSFET with low inter-electrode capacitance is required. The 2N7002 is a good choice.

Figure 14. Self-Synchronizing Setup

7.3.5 Boot-Strap Supply

The LM22672 incorporates a floating high-side gate driver to control the power MOSFET. The supply for this driver is the external boot-strap capacitor connected between the BOOT pin and SW. A good quality 10 nF ceramic capacitor must be connected to these pins with short, wide PCB traces. One reason the regulator imposes a minimum off-time is to ensure that this capacitor recharges every switching cycle. A minimum load of about 5 mA is required to fully recharge the boot-strap capacitor in the minimum off-time. Some of this load can be provided by the output voltage divider, if used.

7.3.6 Internal Loop Compensation

The LM22672 device has internal loop compensation designed to provide a stable regulator over a wide range of external power stage components. The internal compensation of the -ADJ option is optimized for output voltages below 5 V. If an output voltage of 5 V or greater is needed, the -5.0 option with an external resistor divider can be used.

Ensuring stability of a design with a specific power stage (inductor and output capacitor) can be tricky. The LM22672 stability can be verified using the WEBENCH Designer online circuit simulation tool. A quick start spreadsheet can also be downloaded from the online product folder.

The complete transfer function for the regulator loop is found by combining the compensation and power stage transfer functions. The LM22672 has internal type III loop compensation, as detailed in Figure 15. This is the approximate "straight line" function from the FB pin to the input of the PWM modulator. The power stage transfer function consists of a dc gain and a second order pole created by the inductor and output capacitor(s). Due to the input voltage feedforward employed in the LM22672, the power stage dc gain is fixed at 20 dB. The second order pole is characterized by its resonant frequency and its quality factor (Q). For a first pass design, the product of inductance and output capacitance should conform to Equation 4.

Equation 4.

Alternatively, this pole should be placed between 1.5 kHz and 15 kHz and is given by Equation 5.

Equation 5.

The Q factor depends on the parasitic resistance of the power stage components and is not typically in the control of the designer. Of course, loop compensation is only one consideration when selecting power stage components; see the Application Information section for more details.

Figure 15. Compensator Gain

In general, hand calculations or simulations can only aid in selecting good power stage components. Good design practice dictates that load and line transient testing should be done to verify the stability of the application. Also, Bode plot measurements should be made to determine stability margins. AN-1889 How to Measure the Loop Transfer Function of Power Supplies (SNVA364) shows how to perform a loop transfer function measurement with only an oscilloscope and function generator.

7.4.1 Current Limit

The LM22672 device has current limiting to prevent the switch current from exceeding safe values during an accidental overload on the output. This peak current limit is found in the Electrical Characteristics table under the heading of I_CL. The maximum load current that can be provided, before current limit is reached, is determined from Equation 6.

Equation 6.

Where:

L is the value of the power inductor.

When the LM22672 device enters current limit, the output voltage will drop and the peak inductor current will be fixed at I_CL at the end of each cycle. The switching frequency will remain constant while the duty cycle drops. The load current will not remain constant, but will depend on the severity of the overload and the output voltage.

For very severe overloads ("short-circuit"), the regulator changes to a low frequency current foldback mode of operation. The frequency foldback is about 1/5 of the nominal switching frequency. This will occur when the current limit trips before the minimum on-time has elapsed. This mode of operation is used to prevent inductor current "run-away", and is associated with very low output voltages when in overload. Equation 7 can be used to determine what level of output voltage will cause the part to change to low frequency current foldback.

Equation 7.

Where:

F_sw is the normal switching frequency.

V_in is the maximum for the application.

If the overload drives the output voltage to less than or equal to V_x, the part will enter current foldback mode. If a given application can drive the output voltage to ≤ V_x during an overload, then a second criterion must be checked. Equation 8 gives the maximum input voltage, when in this mode, before damage occurs.

Equation 8.

Where:

V_sc is the value of output voltage during the overload.

F_sw is the normal switching frequency.

It is important to note that the voltages in these equations are measured at the inductor. Normal trace and wiring resistance will cause the voltage at the inductor to be higher than that at a remote load. Therefore, even if the load is shorted with zero volts across its terminals, the inductor will still see a finite voltage. It is this value that should be used for V_x and V_sc in the calculations. In order to return from foldback mode, the load must be reduced to a value much lower than that required to initiate foldback. This load "hysteresis" is a normal aspect of any type of current limit foldback associated with voltage regulators.

If the frequency synchronization feature is used, the current limit frequency foldback is not operational, and the system may not survive a hard short-circuit at the output.

The safe operating areas, when in short circuit mode, are shown in Figure 16 through Figure 18 for different switching frequencies. Operating points below and to the right of the curve represent safe operation.

Figure 16. SOA at 300 kHz

Figure 18. SOA at 800 kHz

Figure 17. SOA at 500 kHz

7.4.2 Thermal Protection

Internal thermal shutdown circuitry protects the LM22672 should the maximum junction temperature be exceeded. This protection is activated at about 150°C, with the result that the regulator will shutdown until the temperature drops below about 135°C.

7.4.3 Duty-Cycle Limits

Ideally the regulator would control the duty cycle over the full range of zero to one. However due to inherent delays in the circuitry, there are limits on both the maximum and minimum duty cycles that can be reliably controlled. This in turn places limits on the maximum and minimum input and output voltages that can be converted by the LM22672. A minimum on-time is imposed by the regulator in order to correctly measure the switch current during a current limit event. A minimum off-time is imposed in order the re-charge the bootstrap capacitor. Equation 9 can be used to determine the approximate maximum input voltage for a given output voltage.

Equation 9.

Where:

F_sw is the switching frequency.

T_ON is the minimum on-time.

Both parameters can be found in the Electrical Characteristics table.

If the frequency adjust feature is used, that value should be used for F_sw. Nominal values should be used. The worst case is lowest output voltage and highest switching frequency. If this input voltage is exceeded, the regulator will skip cycles, effectively lowering the switching frequency. The consequences of this are higher output voltage ripple and a degradation of the output voltage accuracy.

The second limitation is the maximum duty cycle before the output voltage will "dropout" of regulation. Equation 10 can be used to approximate the minimum input voltage before dropout occurs.

Equation 10.

Where:

The values of T_OFF and R_DS(ON) are found in the Electrical Characteristics table.

The worst case here is highest switching frequency and highest load. In this equation, R_L is the dc inductor resistance. Of course, the lowest input voltage to the regulator must not be less than 4.5 V (typ).