7.3.1 Current DAC

The LM10011 current DAC is based on a low-voltage bandgap reference setting a current through a precision adjustable resistor. This bandgap is trimmed for precision and gives excellent performance over temperature. The output current has a maximum full-scale range [VID = 000000b] of 59.2 µA and is adjustable with a 6- or 4-bit VID word. This allows for 64 or 16 settings with a resolution of 940 nA or 3.76 µA, respectively. The current DAC also has a slew limit to prevent abrupt changes in the output. The slew limit is represented as a time constant, t₆ = 40 µs, in the Electrical Characteristics table. A deglitch filter for the VID inputs provides noise immunity and effectively adds a small delay from the transition of a VID line to the change in IDAC_OUT current.

7.3.2 Enable Pin and UVLO

The enable (EN) pin allows the output of the device to be enabled or disabled (IDAC_OUT = 0.0 µA) with an external control signal. This pin is a precision analog input that enables the device when the voltage exceeds 1.34 V. The EN pin has 100 mV of hysteresis and will disable the output when the enable voltage falls below 1.23 V. If EN is not used, it can be left open, and will be pulled high by an internal 2-μA current source. Since the EN pin has a precise turn-on threshold it can be used along with an external resistor divider network from VDD to configure the device to turn on at a precise input voltage.

The LM10011 has a built-in undervoltage lockout (UVLO) protection circuit that keeps the device from operating until the input voltage reaches 2.65 V (typical). The UVLO threshold has 200 mV of hysteresis that keeps the LM10011 from responding to power-on glitches during start-up. Note that descending below the EN voltage and/or the UVLO voltage are functionally the same as a reset. Bringing the device back from a low enable setting or from a VDD UVLO event will reset the IDAC_OUT current to its start-up R_SET setting.

Table 1. Mode Pin Summary

7.5.1 VID Programming, 6-Bit Mode

Four pins are used to communicate with the LM10011. In 6-bit mode (MODE = 0), VIDA, VIDB, and VIDC are data lines, while VIDS is a latching strobe that programs in the LM10011 data. As shown in the 6-bit mode timing diagram of Figure 1, the falling edge of VIDS latches in the data from VIDA, VIDB, and VIDC as the lower three LSB of the IDAC_OUT value, [2:0]. After a minimum hold time (t₂), the rising edge of VIDS latches in the data from VIDA, VIDB, and VIDC as the upper three LSB of the IDAC_OUT value, [5:3]. Internally, a delay (t₃,t₁) on VIDS allows for the setting of all VIDA, VIDB, and VIDC lines to change simultaneously as VIDS rises or falls.

7.5.2 VID Programming, 4-Bit Mode

The LM10011 includes a 4-bit mode to facilitate parallel VID communication. In 4-bit mode (MODE = 1), VIDC, VIDB, VIDA, and VIDS are all parallel data lines. As shown in the 4-bit mode timing diagram in Figure 1, a changing edge of any of the VID communication lines will change the IDAC_OUT current to the corresponding new 4-bit value found on the data lines. There is a 3-μs deglitch filter to eliminate spurious noise events. The data must overcome the deglitch time and the minimum hold time (t₇) or else the IDAC_OUT pin current may not reflect the value indicated at the VID data inputs. During the hold time, no other data line can be transitioned.

As mentioned in a previous section, for both the 4-bit and 6-bit mode, the VID data word is set so that the lowest output current is seen at the highest VID data word (59.2 µA at a code of 0d in 6-bit mode and 56.4 µA in 4-bit mode). Conversely, the lowest current is seen at the highest VID data word (0.06 µA at 63d or 15d). During VID operation with the regulator, this will translate to the lowest output voltage with the lowest VID word, 0d, and the highest output voltage with the highest VID word, 63d or 15d. The communications pins can be used with a low-voltage microcontroller with a maximum V_IL of 0.75 V and a minimum V_IH of 1.0 V.

7.5.3 Programming the Start-Up Current

Depending on the value of R_SET during start-up (when VDD > VUVLO_R and EN > VEN), the output current on the IDAC_OUT pin will take on 1 of 16 discrete values corresponding to the currents available in the 4-bit mode. These discrete start-up currents can be programmed by connecting a resistor (R_SET) from the SET pin to GND. If the EN voltage is toggled or a UVLO is triggered during operation, the current will default back to the value set by the R_SET resistor. It takes only one VID command transition in either 4-bit or 6-bit mode to change the current to something other than the pre-programmed start-up current. The required R_SET resistors and their corresponding start-up currents codes can be found in Table 2.

Codes 0100b (4d) through 1110b (14d) will start-up into either the selected code or 1 code higher. This means that the output voltage of the POL may start-up into the selected output voltage or 1 LSB higher.

7.5.4 IDAC_OUT Current Values