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ZHCS455F December 2010 – July 2015 ISO7420E , ISO7420FE , ISO7421E , ISO7421FE

PRODUCTION DATA.

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訂購(gòu)信息

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

		MIN	MAX	UNIT
V_CC	Supply voltage⁽²⁾, V_CC1, V_CC2	–0.5	6	V
V_I	Voltage at IN, OUT	–0.5	V_CC + 0.5⁽³⁾	V
I_O	Output current		±15	mA
V_SRG	Maximum surge immunity - Supports IEC 61000-4-5		4000	V_PK
T_J(Max)	Maximum junction temperature		150	°C
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal and are peak voltage values.

(3) Maximum voltage must not exceed 6 V.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±3000	V
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500
		Machine model (MM) ANSI/ESDS5.2-1996	±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
V_CC1, V_CC2	Supply voltage	3.0		5.5	V
I_OH	High-level output current	–4			mA
I_OL	Low-level output current			4	mA
V_IH	High-level input voltage	2		5.5	V
V_IL	Low-level input voltage	0		0.8	V
t_ui	Input pulse duration	20			ns
1 / t_ui	Signaling rate	0		50⁽²⁾	Mbps
T_J⁽¹⁾	Junction temperature	–40		136	°C
T_A	Ambient Temperature	-40	25	125	°C

(1) To maintain the recommended operating conditions for T_J, see the Thermal Information table.

(2) Under typical conditions, these devices are capable of signaling rate > 150 Mbps.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾			ISO742x	UNIT
			D (SOIC)
			8 PINS
R_θJA	Junction-to-ambient thermal resistance	Low-K board	212	°C/W
R_θJA	Junction-to-ambient thermal resistance	High-K board	116.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance		71.6	°C/W
R_θJB	Junction-to-board thermal resistance		57.3	°C/W
ψ_JT	Junction-to-top characterization parameter		28.3	°C/W
ψ_JB	Junction-to-board characterization parameter		56.8	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics: V_CC1 and V_CC2 = 5 V ± 10%

T_A = –40°C to 125°C

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –4 mA; see Figure 16.		V_CCO⁽¹⁾– 0.8	4.6		V
V_OH	High-level output voltage	I_OH= –20 μA; see Figure 16.		V_CCO– 0.1	5		V
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 16.			0.2	0.4	V
V_OL	Low-level output voltage	I_OL = 20 μA; see Figure 16.			0	0.1	V
V_I(HYS)	Input threshold voltage hysteresis				400		mV
I_IH	High-level input current	INx at 0 V or V_CCI⁽¹⁾				10	μA
I_IL	Low-level input current	INx at 0 V or V_CCI⁽¹⁾		–10			μA
CMTI	Common-mode transient immunity	V_I = V_CCI or 0 V; see Figure 18.		25	50		kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC I_CC MEASUREMENT)
	ISO7420x
I_CC1	Supply current for V_CC1 and V_CC2	DC to 1 Mbps	DC Input: V_I = V_CCI or 0 V, AC Input: C_L = 15 pF		0.4	0.8	mA
I_CC2		DC to 1 Mbps	DC Input: V_I = V_CCI or 0 V, AC Input: C_L = 15 pF		3.4	5
I_CC1		10 Mbps	C_L = 15 pF		0.6	1
I_CC2		10 Mbps			4.5	6
I_CC1		25 Mbps			1	1.5
I_CC2		25 Mbps			6.2	8
I_CC1		50 Mbps			1.7	2.5
I_CC2		50 Mbps			9	12
	ISO7421x
I_CC1	Supply current for V_CC1 and V_CC2	DC to 1 Mbps	DC Input: V_I = V_CCI or 0 V, AC Input: C_L = 15 pF		2.3	3.6	mA
I_CC2		DC to 1 Mbps	DC Input: V_I = V_CCI or 0 V, AC Input: C_L = 15 pF		2.3	3.6
I_CC1		10 Mbps	C_L = 15 pF		2.9	4.5
I_CC2		10 Mbps			2.9	4.5
I_CC1		25 Mbps			4.3	6
I_CC2		25 Mbps			4.3	6
I_CC1		50 Mbps			6	8.5
I_CC2		50 Mbps			6	8.5

(1) V_CCI = Input-side V_CC; V_CCO = Output-side V_CC

6.6 Electrical Characteristics: V_CC1 = 5 V ± 10%, V_CC2 = 3.3 V ± 10%

T_A = –40°C to 125°C

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –4 mA; see Figure 16.	ISO7421x (5-V side)	V_CC1 – 0.8	4.6		V
		I_OH = –4 mA; see Figure 16.	ISO7420x/7421x (3.3-V side)	V_CC2 - 0.4	3
		I_OH= –20 μA; see Figure 16,	ISO7421x (5-V side)	V_CC1 – 0.1	5
		I_OH= –20 μA; see Figure 16,	ISO7420x/7421x (3.3-V side)	V_CC2 – 0.1	3.3
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 16.			0.2	0.4	V
V_OL	Low-level output voltage	I_OL = 20 μA; see Figure 16.			0	0.1	V
V_I(HYS)	Input threshold voltage hysteresis				400		mV
I_IH	High-level input current	INx at 0 V or V_CCI				10	μA
I_IL	Low-level input current	INx at 0 V or V_CCI		–10			μA
CMTI	Common-mode transient immunity	V_I = V_CCI or 0 V; see Figure 18.		25	50		kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC I_CC MEASUREMENT)
	ISO7420x
I_CC1	Supply current for V_CC1 and V_CC2	DC to 1 Mbps	DC Input: V_I = V_CCI or 0 V, AC Input: C_L = 15 pF		0.4	0.8	mA
I_CC2		DC to 1 Mbps	DC Input: V_I = V_CCI or 0 V, AC Input: C_L = 15 pF		2.6	3.7
I_CC1		10 Mbps	C_L = 15 pF		0.6	1
I_CC2		10 Mbps			3.3	4.3
I_CC1		25 Mbps			1	1.5
I_CC2		25 Mbps			4.4	5.6
I_CC1		50 Mbps			1.7	2.5
I_CC2		50 Mbps			6.2	7.5
	ISO7421x
I_CC1	Supply current for V_CC1 and V_CC2	DC to 1 Mbps	DC Input: V_I = V_CCI or 0 V, AC Input: C_L = 15 pF		2.3	3.6	mA
I_CC2		DC to 1 Mbps	DC Input: V_I = V_CCI or 0 V, AC Input: C_L = 15 pF		1.8	2.8
I_CC1		10 Mbps	C_L = 15 pF		2.9	4.5
I_CC2		10 Mbps			2.2	3.2
I_CC1		25 Mbps			4.3	6
I_CC2		25 Mbps			2.8	4.1
I_CC1		50 Mbps			6	8.5
I_CC2		50 Mbps			3.8	5.5

6.7 Electrical Characteristics: V_CC1 = 3.3 V ± 10%, V_CC2 = 5 V ± 10%

T_A = –40°C to 125°C

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –4 mA; see Figure 16.	ISO7421x (3.3-V side)	V_CC1 – 0.4	3		V
		I_OH = –4 mA; see Figure 16.	ISO7420x/7421x (5-V side)	V_CC2 – 0.8	4.6
		I_OH= –20 μA; see Figure 16	ISO7421x (3.3-V side)	V_CC1 – 0.1	3.3
		I_OH= –20 μA; see Figure 16	ISO7420x/7421x (5-V side)	V_CC2 – 0.1	5
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 16.			0.2	0.4	V
V_OL	Low-level output voltage	I_OL = 20 μA; see Figure 16.			0	0.1	V
V_I(HYS)	Input threshold voltage hysteresis				400		mV
I_IH	High-level input current	INx at 0 V or V_CCI				10	μA
I_IL	Low-level input current	INx at 0 V or V_CCI		–10			μA
CMTI	Common-mode transient immunity	V_I = V_CCI or 0 V; see Figure 18.		25	50		kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC I_CC MEASUREMENT)
	ISO7420x
I_CC1	Supply current for V_CC1 and V_CC2	DC to 1 Mbps	DC Input: V_I = V_CCI or 0 V, AC Input: C_L = 15 pF		0.2	0.4	mA
I_CC2		DC to 1 Mbps	DC Input: V_I = V_CCI or 0 V, AC Input: C_L = 15 pF		3.4	5
I_CC1		10 Mbps	C_L = 15 pF		0.4	0.6
I_CC2		10 Mbps			4.5	6
I_CC1		25 Mbps			0.6	0.9
I_CC2		25 Mbps			6.2	8
I_CC1		50 Mbps			1	1.3
I_CC2		50 Mbps			9	12
	ISO7421x
I_CC1	Supply current for V_CC2 and V_CC2	DC to 1 Mbps	DC Input: V_I = V_CCI or 0 V, AC Input: C_L = 15 pF		1.8	2.8	mA
I_CC2		DC to 1 Mbps	DC Input: V_I = V_CCI or 0 V, AC Input: C_L = 15 pF		2.3	3.6
I_CC1		10 Mbps	C_L = 15 pF		2.2	3.2
I_CC2		10 Mbps			2.9	4.5
I_CC1		25 Mbps			2.8	4.1
I_CC2		25 Mbps			4.3	6
I_CC1		50 Mbps			3.8	5.5
I_CC2		50 Mbps			6	8.5

6.8 Electrical Characteristics: V_CC1 and V_CC2 = 3.3 V ± 10%

T_A = –40°C to 125°C

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –4 mA; see Figure 16.		V_CCO⁽¹⁾ – 0.4	3		V
V_OH	High-level output voltage	I_OH= –20 μA; see Figure 16.		V_CCO – 0.1	3.3		V
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 16.			0.2	0.4	V
V_OL	Low-level output voltage	I_OL = 20 μA; see Figure 16.			0	0.1	V
V_I(HYS)	Input threshold voltage hysteresis				400		mV
I_IH	High-level input current	INx at 0 V or V_CCI⁽¹⁾				10	μA
I_IL	Low-level input current	INx at 0 V or V_CCI⁽¹⁾		–10			μA
CMTI	Common-mode transient immunity	V_I = V_CCI or 0 V; see Figure 18.		25	50		kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC I_CC MEASUREMENT)
	ISO7420x
I_CC1	Supply current for V_CC1 and V_CC2	DC to 1 Mbps	DC Input: V_I = V_CCI or 0 V, AC Input: C_L = 15 pF		0.2	0.4	mA
I_CC2		DC to 1 Mbps	DC Input: V_I = V_CCI or 0 V, AC Input: C_L = 15 pF		2.6	3.7
I_CC1		10 Mbps	C_L = 15 pF		0.4	0.6
I_CC2		10 Mbps			3.3	4.3
I_CC1		25 Mbps			0.6	0.9
I_CC2		25 Mbps			4.4	5.6
I_CC1		50 Mbps			1	1.3
I_CC2		50 Mbps			6.2	7.5
	ISO7421x
I_CC1	Supply current for V_CC2 and V_CC2	DC to 1 Mbps	DC Input: V_I = V_CCI or 0 V, AC Input: C_L = 15 pF		1.8	2.8	mA
I_CC2		DC to 1 Mbps	DC Input: V_I = V_CCI or 0 V, AC Input: C_L = 15 pF		1.8	2.8
I_CC1		10 Mbps	C_L = 15 pF		2.2	3.2
I_CC2		10 Mbps			2.2	3.2
I_CC1		25 Mbps			2.8	4.1
I_CC2		25 Mbps			2.8	4.1
I_CC1		50 Mbps			3.8	5.5
I_CC2		50 Mbps			3.8	5.5

(1) V_CCI = Input-side V_CC; V_CCO = Output-side V_CC

6.9 Power Dissipation Characteristics

THERMAL METRIC			ISO742x	UNIT
			D (SOIC)
			8 PINS
P_D	Device power dissipation	V_CC1 = V_CC2 = 5.5 V, T_J = 150°C, C_L = 15 pF, Input a 100-Mbps 50% duty-cycle square wave	138	mW

6.10 Switching Characteristics: V_CC1 and V_CC2 = 5 V ± 10%

T_A = –40°C to 125°C

PARAMETER			TEST CONDITIONS	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time		See Figure 16.	7	11	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	ISO7420x		0.2	3	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	ISO7421x		0.3	3.7	ns
t_sk(o)⁽²⁾	Channel-to-channel output skew time	ISO7420x		0.3	1	ns
t_sk(o)⁽²⁾	Channel-to-channel output skew time	ISO7421x		0.3	2	ns
t_sk(pp)⁽³⁾	Part-to-part skew time	ISO7420x			3.7	ns
t_sk(pp)⁽³⁾	Part-to-part skew time	ISO7421x			4.9	ns
t_r	Output signal rise time		See Figure 16.	1.8		ns
t_f	Output signal fall time		See Figure 16.	1.7		ns
t_fs	Fail-safe output delay time from input power loss		See Figure 17.	6		μs

(1) Also known as pulse skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.

(3) t_sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.11 Switching Characteristics: V_CC1 = 5 V ± 10%, V_CC2 = 3.3 V ± 10%

T_A = –40°C to 125°C

PARAMETER			TEST CONDITIONS	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time		See Figure 16.	8	13.5	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	ISO7420x		0.3	3	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	ISO7421x		0.5	5.6	ns
t_sk(o)⁽²⁾	Channel-to-channel output skew time	ISO7420x			1.5	ns
t_sk(o)⁽²⁾	Channel-to-channel output skew time	ISO7421x		0.5	3	ns
t_sk(pp)⁽³⁾	Part-to-part skew time	ISO7420x			5.4	ns
t_sk(pp)⁽³⁾	Part-to-part skew time	ISO7421x			6.3	ns
t_r	Output signal rise time		See Figure 16.	2		ns
t_f	Output signal fall time		See Figure 16.	2		ns
t_fs	Fail-safe output delay time from input power loss		See Figure 17.	6		μs

(1) Also known as pulse skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.

6.12 Switching Characteristics: V_CC1 = 3.3 V ± 10%, V_CC2 = 5 V ± 10%

T_A = –40°C to 125°C

PARAMETER			TEST CONDITIONS	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time	ISO7420x	See Figure 16.	7.5	12	ns
t_PLH, t_PHL	Propagation delay time	ISO7421x		7.5	14	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	ISO7420x		0.7	3	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	ISO7421x		0.7	3.6	ns
t_sk(o)⁽²⁾	Channel-to-channel output skew time	ISO7420x		0.5	1.5	ns
t_sk(o)⁽²⁾	Channel-to-channel output skew time	ISO7421x		0.5	3	ns
t_sk(pp)⁽³⁾	Part-to-part skew time	ISO7420x			4.6	ns
t_sk(pp)⁽³⁾	Part-to-part skew time	ISO7421x			8.5	ns
t_r	Output signal rise time		See Figure 16.	1.7		ns
t_f	Output signal fall time		See Figure 16.	1.6		ns
t_fs	Fail-safe output delay time from input power loss		See Figure 17.	6		μs

(1) Also known as pulse skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.

6.13 Switching Characteristics: V_CC1 and V_CC2 = 3.3 V ± 10%

T_A = –40°C to 125°C

PARAMETER			TEST CONDITIONS	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time		See Figure 16	8.5	14	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	ISO7420x and ISO7421x	See Figure 16	0.5	2	ns
t_sk(o)⁽²⁾	Channel-to-channel output skew time	ISO7420x		0.4	2	ns
t_sk(o)⁽²⁾	Channel-to-channel output skew time	ISO7421x		0.4	3	ns
t_sk(pp)⁽³⁾	Part-to-part skew time	ISO7420x			6.2	ns
t_sk(pp)⁽³⁾	Part-to-part skew time	ISO7421x			6.8	ns
t_r	Output signal rise time		See Figure 16	2		ns
t_f	Output signal fall time		See Figure 16	1.8		ns
t_fs	Fail-safe output delay time from input power loss		See Figure 17	6		μs

(1) Also known as pulse skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.