SLLSFC2D December 2020 – September 2021 ISO1640 , ISO1641 , ISO1642 , ISO1643 , ISO1644
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| ISO1640 | ||||||
| PD | Maximum power dissipation (both sides) | VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 = 1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal | 96 | mW | ||
| PD1 | Maximum power dissipation (side-1) | 43 | mW | |||
| PD2 | Maximum power dissipation (side-2) | 53 | mW | |||
| ISO1641 | ||||||
| PD | Maximum power dissipation (both sides) | VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 = 1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal | 87 | mW | ||
| PD1 | Maximum power dissipation (side-1) | VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 = 1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal | 40 | mW | ||
| PD2 | Maximum power dissipation (side-2) | VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 = 1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal | 47 | mW | ||
| ISO1642 | ||||||
| PD | Maximum power dissipation (both sides) | VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 = 1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal INA = INB = Input at 25-MHz 50% duty cycle square wave, CL = 15pF |
185 | mW | ||
| PD1 | Maximum power dissipation (side-1) | 83 | mW | |||
| PD2 | Maximum power dissipation (side-2) | 102 | mW | |||
| ISO1643 | ||||||
| PD | Maximum power dissipation (both sides) | VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 = 1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal INA = INB = Input at 25-MHz 50% duty cycle square wave, CL = 15pF |
185 | mW | ||
| PD1 | Maximum power dissipation (side-1) | 67 | mW | |||
| PD2 | Maximum power dissipation (side-2) | 118 | mW | |||
| ISO1644 | ||||||
| PD | Maximum power dissipation (both sides) | VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 = 1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal INA = INB = INC = Input at 25-MHz 50% duty cycle square wave, CL = 15pF |
210 | mW | ||
| PD1 | Maximum power dissipation (side-1) | 88 | mW | |||
| PD2 | Maximum power dissipation (side-2) | 122 | mW | |||