SLLSFC3A March 2020 – December 2021 ISO1640-Q1
PRODUCTION DATA
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Ratings
- Insulation Specifications
- 6.6 Safety-Related Certifications
- 6.7 Safety Limiting Values
- 6.8 Electrical Characteristics
- 6.9 Supply Current Characteristics
- 6.10 Timing Requirements
- 6.11 Switching Characteristics
- 6.12 Insulation Characteristics Curves
- 6.13 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.5 Isolator Functional Principle
To isolate a bidirectional signal path (SDA or SCL), the ISO1640-Q1 internally splits a bidirectional line into two unidirectional signal lines, each of which is isolated through a single-channel digital isolator. Each channel output is made open-drain to comply with the open-drain technology of I2C. Side 1 of the ISO1640-Q1 connects to a low-capacitance I2C node (up to 80 pF), while side 2 is designed for connecting to a fully loaded I2C bus with up to 400 pF of capacitance.
Figure 8-2 SDA Channel Design and Voltage Levels at SDA1At first sight, the arrangement of the internal buffers suggests a closed signal loop that is prone to latch-up. However, this loop is broken by implementing an output buffer (B) whose output low-level is raised by a diode drop to approximately 0.65 V, and the input buffer (C) that consists of a comparator with defined hysteresis. The comparator’s upper and lower input thresholds then distinguish between the proper low-potential of 0.4 V (maximum) driven directly by SDA1 and the buffered output low-level of B.
Figure 8-3 demonstrate the switching behavior of the I2C isolator, ISO164x-Q1, between a master node at SDA1 and a heavy loaded bus at SDA2.
Figure 8-3 SDA Channel Timing in Receive and Transmit Directions