ZHCSSZ4H October 2010 – August 2023 ISO1176T
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Ratings
- 6.6 Insulation Specifications
- 6.7 Safety-Related Certifications
- 6.8 Safety Limiting Values
- 6.9 Electrical Characteristics: ISODE-Pin
- 6.10 Electrical Characteristics: Driver
- 6.11 Electrical Characteristics: Receiver
- 6.12 Supply Current
- 6.13 Transformer Driver Characteristics
- 6.14 Switching Characteristics: Driver
- 6.15 Switching Characteristics: Receiver
- 6.16 Insulation Characteristics Curves
- 6.17 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
Figure 7-1 Open Circuit Voltage Test Circuit
Figure 7-2 VOD Test Circuit
Figure 7-3 Driver VOD with Common-mode Loading Test Circuit
Figure 7-4 Driver VOD and VOC Without Common-Mode Loading Test Circuit
Figure 7-5 Steady-State Output Voltage Test Circuit and Voltage Waveforms
Figure 7-6 VOD(RING) Waveform and Definitions
Figure 7-7 Input Voltage Hysteresis Test Circuit
Figure 7-8 Driver Short-Circuit Test Circuit and Waveforms (Short Circuit applied at Time t=0)
Figure 7-9 Driver Switching Test Circuit and Waveforms
Figure 7-10 Driver Output Transition Skew Test Circuit and Waveforms
Figure 7-11 Driver Enable/Disable Test, D at Logic Low Test Circuit and Waveforms
Figure 7-12 Driver Enable/Disable Test, D at Logic High Test Circuit and Waveforms
Figure 7-13 DE to ISODE Prop Delay Test Circuit and Waveforms
Figure 7-14 Receiver DC Parameter Definitions
Figure 7-15 Receiver Switching Test Circuit and Waveforms
Figure 7-16 Receiver Enable Test Circuit and Waveforms, Data Output High
Figure 7-17 Receiver Enable Test Circuit and Waveforms, Data Output Low
Figure 7-18 Common-Mode Rejection Test Circuit
Figure 7-19 Common-Mode Transient Immunity Test Circuit
Figure 7-20 Transition Times and Break-Before-Make Time Delay for D1, D2 Outputs