ZHCSFN6F March 2007 – June 2021 INA203 , INA204 , INA205
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|---|---|
| OFFSET VOLTAGE | ||||||||
| Offset Voltage | Comparator Common-Mode Voltage = Threshold Voltage | 2 | mV | |||||
| Offset Voltage Drift, Comparator 1 | TA = –40°C to 125°C | ±2 | μV/°C | |||||
| Offset Voltage Drift, Comparator 2 | TA = –40°C to 125°C | 5.4 | μV/°C | |||||
| Threshold | TA = 25°C | 590 | 608 | 620 | mV | |||
| Threshold over Temperature | TA = –40°C to 125°C | 586 | 625 | mV | ||||
| Hysteresis (1), CMP1 | TA = –40°C to 85°C | –8 | mV | |||||
| Hysteresis (1), CMP2 | TA = –40°C to 85°C | 8 | mV | |||||
| INPUT BIAS CURRENT (2) | ||||||||
| CMP1 IN+, CMP2 IN+ | 0.005 | 10 | nA | |||||
| CMP1 IN+, CMP2 IN+ vs. Temperature | TA = –40°C to 125°C | 15 | nA | |||||
| INPUT IMPEDANCE | ||||||||
| Pins 3 and 6 (14-pin packages only) | 10 | k? | ||||||
| INPUT RANGE | ||||||||
| CMP1 IN+ and CMP2 IN+ | 0 V to VS – 1.5 V | V | ||||||
| Pins 3 and 6 (14-pin packages only) (3) | 0 V to VS – 1.5 V | V | ||||||
| OUTPUT | ||||||||
| Large-Signal Differential Voltage Gain | CMP VOUT 1 V to 4 V, RL ≥ 15 k? Connected to 5 V | 200 | V/mV | |||||
| High-Level Output Current | VID = 0.4 V, VOH = VS | 0.0001 | 1 | μA | ||||
| Low-Level Output Voltage | VID = –0.6 V, IOL = 2.35 mA | 220 | 300 | mV | ||||
| RESPONSE TIME (4) | ||||||||
| Comparator 1 | RL to 5 V, CL = 15 pF, 100-mV Input Step with 5-mV Overdrive | 1.3 | μs | |||||
| Comparator 2 | RL to 5 V, CL = 15 pF, 100-mV Input Step with 5-mV Overdrive, CDELAY Pin Open | 1.3 | μs | |||||
| RESET | ||||||||
| RESET Threshold (5) | 1.1 | V | ||||||
| Logic Input Impedance | 2 | M? | ||||||
| Minimum RESET Pulse Width | 1.5 | μs | ||||||
| RESET Propagation Delay | 3 | μs | ||||||
| Comparator 2 Delay Equation (6) | CDELAY = tD/5 | μF | ||||||
| tD | Comparator 2 Delay | CDELAY = 0.1 μF | 0.5 | s | ||||
Figure 6-1 Comparator Hysteresis