ZHCSJN1C September 2000 – September 2022 INA118
PRODUCTION DATA
Section 8.2 shows a simplified representation of the INA118 and provides insight into device operation. Each input is protected by two FET transistors that provide a low series resistance under normal signal conditions, thus preserving excellent noise performance. When excessive voltage is applied, these transistors limit input current to approximately 6 mA.
The differential input voltage is buffered by Q1 and Q2 and impressed across RG, causing a signal current to flow through RG, R1, and R2. The output difference amp, A3, removes the common-mode component of the input signal and refers the output signal to the Ref pin.