7.3.1 Data Transfer

The DS92LV242x chipset transmits and receives a pixel of data in the following format: C1 and C0 represent the embedded clock in the serial stream. C1 is always high and C0 is always low. The b[23:0] contains the scrambled LVCMOS data. DCB is the DC-Balanced control bit. DCB is used to minimize the short and long-term DC bias on the signal lines. This bit determines if the data is unmodified or inverted. DCA is used to validate data integrity in the embedded data stream and can also contain encoded control (VS, HS, DE). Both DCA and DCB coding schemes are generated by the serializer and decoded by the deserializer automatically. Figure 23 illustrates the serial stream per clock cycle.

Figure 23. Channel Link II Serial Stream (DS92LV242x)

7.3.2 Video Control Signal Filter – Serializer and Deserializer

When operating the devices in normal mode, the video control signals (DE, HS, VS) have the following restrictions:

• Normal mode with control signal filter enabled:
  • DE and HS: Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3 CLK cycles or longer.
• Normal mode with control signal filter disabled:
  • DE and HS: Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition pulse.
• VS: Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.

Video control signals are defined as low frequency signals with limited transitions. Glitches of a control signal can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency noise on the control signals (see Figure 24).

Figure 24. Video Control Signal Filter Waveform

7.3.3 Serializer Functional Description

The serializer converts a wide parallel input bus to a single serial output data stream and also acts as a signal generator for the chipset Built In Self Test (BIST) mode. The device can be configured through external pins or through the optional serial control bus. The serializer features enhance signal quality on the link by supporting: a selectable VOD level, a selectable de-emphasis signal conditioning, and Channel Link II data coding that provides randomization, scrambling, and DC balancing of the data. The serializer includes multiple features to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the data and system spread spectrum clock support. The serializer features power-saving features with a sleep mode, auto stop clock feature, and optional LVCMOS (1.8 V) parallel bus compatibility (see also Optional Serial Bus Control and Built-In Self Test (BIST)).

7.3.3.2 Signal Quality Enhancers

7.3.3.2.1 Serializer VOD Select (VODSEL)

The serializer differential output voltage may be increased by setting the VODSEL pin high. When VODSEL is low, the DC VOD is at the standard (default) level. When VODSEL is high, the VOD is increased in level. The increased VOD is useful in extremely high noise environments and also on extra long cable length applications. When using de-emphasis, TI recommends setting VODSEL = H to avoid excessive signal attenuation, especially with the larger de-emphasis settings. This feature may be controlled by the external pin or by register.

Table 2. Differential Output Voltage

INPUT	EFFECT
VODSEL	VOD (mV)	VOD (mVp-p)
H	±420	840
L	±280	560

7.3.3.2.2 Serializer De-Emphasis (De-Emph)

The de-emphasis pin controls the amount of de-emphasis beginning one full bit time after a logic transition that the serializer drives. This is useful to counteract loading effects of long or lossy cables. This pin must be left open for standard switching currents (no de-emphasis) or if controlled by register. De-emphasis is selected by connecting a resistor on this pin to ground, with R value between 0.5 kΩ to 1 MΩ, or by register setting. When using de-emphasis, TI recommends to set VODSEL = H.

Table 3. De-Emphasis Resistor Value

RESISTOR VALUE (kΩ)	DE-EMPHASIS SETTING
Open	Disabled
0.6	–12 dB
1	–9 dB
2	–6 dB
5	–3 dB

Figure 25. De-Emphasis vs R Value

7.3.4 Deserializer Functional Description

The deserializer converts a single input serial data stream to a wide parallel output bus and also provides a signal check for the chipset Built-In Self Test (BIST) mode. The device can be configured through external pins and strap pins or through the optional serial control bus. The deserializer features enhance signal quality on the link by supporting an equalizer input and Channel Link II data coding that provides randomization, scrambling, and DC balancing of the data. The deserializer includes multiple features to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the data and output spread spectrum clock generation (SSCG) support. The deserializer features power-saving features with a power-down mode and optional LVCMOS (1.8 V) interface compatibility.

7.3.4.2 EMI Reduction Features

7.3.4.2.1 Deserializer Output Slew Rate Select (OS_CLKOUT/OS_DATA)

The parallel bus outputs (DO[23:0], CO[3:1], and CLKOUT) of the deserializer feature a selectable output slew. The DATA (DO[23:0], CO[3:1]) are controlled by strap pin or register bit OS_DATA. The CLKOUT is controlled by strap pin or register bit OS_CLKOUT. When the OS_CLKOUT/DATA = H, the maximum slew rate is selected. When the OS_PCLK/DATA = L, the minimum slew rate is selected. Use the higher slew rate setting when driving longer traces or a heavier capacitive load.

7.3.4.2.2 Deserializer Common-Mode Filter Pin (CMF) (Optional)

The deserializer provides access to the center tap of the internal termination. A capacitor may be placed on this pin for additional common-mode filtering of the differential pair. This can be useful in high-noise environments for additional noise rejection capability. A 4.7-µF capacitor may be connected from this pin to Ground.

7.3.4.2.3 Deserializer SSCG Generation (Optional)

The deserializer provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and data outputs are modulated. This aids to lower system EMI. Output SSCG deviations of ±2% (4% total) at up to 100-kHz modulations are available (see Table 5). This feature may be controlled by external strap pins or by register.

NOTE

The device supports SSCG function with CLKOUT = 10 MHz to 65 MHz. When the CLKOUT = 65 MHz to 75 MHz, it is required to disable the SSCG function (SSC[3:0] = 0000).

Figure 26. SSCG Waveform

Table 5. SSCG Configuration (LF_MODE = L) – Deserializer Output

SSC[3:0] INPUTS LF_MODE = L (20 - 65 MHz)				RESULT
SSC3	SSC2	SSC1	SSC0	fdev (%)	fmod (kHz)
L	L	L	L	Off	Off
L	L	L	H	±0.5	CLK/2168
L	L	H	L	±1
L	L	H	H	±1.5
L	H	L	L	±2
L	H	L	H	±0.5	CLK/1300
L	H	H	L	±1
L	H	H	H	±1.5
H	L	L	L	±2
H	L	L	H	±0.5	CLK/868
H	L	H	L	±1
H	L	H	H	±1.5
H	H	L	L	±2
H	H	L	H	±0.5	CLK/650
H	H	H	L	±1
H	H	H	H	±1.5

Table 6. SSCG Configuration (LF_MODE = H) – Deserializer Output

SSC[3:0] INPUTS LF_MODE = H (10 - 20 MHz)				RESULT
SSC3	SSC2	SSC1	SSC0	fdev (%)	fmod (kHz)
L	L	L	L	Off	Off
L	L	L	H	±0.5	CLK/620
L	L	H	L	±1
L	L	H	H	±1.5
L	H	L	L	±2
L	H	L	H	±0.5	CLK/370
L	H	H	L	±1
L	H	H	H	±1.5
H	L	L	L	±2
H	L	L	H	±0.5	CLK/258
H	L	H	L	±1
H	L	H	H	±1.5
H	H	L	L	±2
H	H	L	H	±0.5	CLK/192
H	H	H	L	±1
H	H	H	H	±1.5

7.3.4.2.4 1.8-V or 3.3-V VDDIO Operation

The deserializer parallel bus and serial bus interface can operate with 1.8-V or 3.3-V levels (V_DDIO) for target (display) compatibility. The 1.8-V levels offer a lower noise (EMI) and also system power savings.

7.3.4.4 Deserializer Oscillator Output (Optional)

The deserializer provides an optional clock output when the input clock (serial stream) has been lost. This is based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled by the external pin or by register (see Table 8 and Table 9).

Table 7. OSS_SEL and PDB Configuration (Deserializer Outputs)

INPUTS			OUTPUTS
SERIAL INPUT	PDB	OSS_SEL	CLKOUT	DO[23:0], CO1, CO2, CO3	LOCK	PASS
X	L	L	Z	Z	Z	Z
X	L	H	Z	Z	Z	Z
Static	H	L	L	L	L	L
Static	H	H	Z	Z(1)	L	L
Active	H	X	Active	Active	H	H

(1) If DO[23:0], CO[3:1] pin is strapped high, the output is pulled up.

Table 8. OSC (Oscillator) Mode — Deserializer Output

INPUTS	OUTPUTS
EMBEDDED CLK	CLKOUT	DO[23:0], CO1, CO2, CO3	LOCK	PASS
See (1)	OSC Output	L	L	H
Present	Toggling	Active	H	H

(1) Absent and OSC_SEL ≠ 000.

Figure 27. Deserializer Outputs With Output State Select Low (OSS_SEL = L)

Figure 28. Deserializer Outputs With Output State Select High (OSS_SEL = H)

Table 9. OSC_SEL (Oscillator) Configuration

OSC_SEL[2:0] INPUTS			CLKOUT OSCILLATOR FREQUENCY
OSC_SEL2	OSC_SEL1	OSC_SEL0
L	L	L	Off – Feature Disabled – Default
L	L	H	50 MHz ± 40%
L	H	L	25 MHz ± 40%
L	H	H	16.7 MHz ± 40%
H	L	L	12.5 MHz ± 40%
H	L	H	10 MHz ± 40%
H	H	L	8.3 MHz ± 40%
H	H	H	6.3 MHz ± 40%

Figure 29. Deserializer Outputs With Output State High and CLKOUT Oscillator Option Enabled

7.3.4.5 Deserializer OP_LOW (Optional)

The OP_LOW feature is used to hold the LVCMOS outputs (except for the LOCK output) at a low state. The user must toggle the OP_LOW set / reset register bit to release the outputs to the normal toggling state.

NOTE

The release of the outputs can only occur when LOCK is high. When the OP_LOW feature is enabled, anytime LOCK = low, the LVCMOS outputs toggle to a low state again. The OP_LOW strap pin feature is assigned to output PASS pin 42.

Restrictions on other straps:

1. Other straps must not be used to keep the data and clock outputs at a true low state. Other features must be selected through I²C.
2. The OSS_SEL function is not available when OP_LOW is enabled (tied high).

Outputs DO[23:0], CO[3:1], and CLKOUT are in TRI-STATE before PDB toggles high, because the OP_LOW strap value has not been recognized until the DS92LV2422 powers up. Figure 30 shows the user controlled release of OP_LOW and automatic reset of OP_LOW set on the falling edge of LOCK. Figure 31 shows the user controlled release of OP_LOW and manual reset of OP_LOW set.

NOTE

Manual reset of OP_LOW can only occur when LOCK is high.

Figure 30. OP_LOW Auto Set

Figure 31. OP_LOW Manual Set or Reset

7.3.5 Built-In Self Test (BIST)

An optional At-Speed Built-In Self Test (BIST) feature supports the testing of the high-speed serial link. This is useful in the prototype stage, equipment production, in-system test, and for system diagnostics. In BIST mode, only an input clock is required along with control to the serializer and deserializer BISTEN input pins. The serializer outputs a test pattern (PRBS-7) and drives the link at speed. The deserializer detects the PRBS-7 pattern and monitors it for errors. A PASS output pin toggles to flag any payloads that are received with 1 to 24 errors. Upon completion of the test, the result of the test is held on the PASS output until reset (new BIST test or power down). A high on PASS indicates NO ERRORS were detected. A low on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin. During the BIST duration, the deserializer data outputs toggle with a checkerboard pattern.

Inter-operability is supported between this Channel Link II device and all Channel Link II generations (Gen 1, 2, 3). See Sample BIST Sequence for entering BIST mode and control.

7.3.5.1 Sample BIST Sequence

See Figure 32 for the BIST mode flow diagram.

Step 1: Place the DS92LV2421 serializer in BIST Mode by setting serializer BISTEN = H. For the DS92LV2421 serializer or DS99R421-Q1 FPD-Link II serializer, BIST Mode is enabled through the BISTEN pin. For the DS90C241 serializer or DS90UR241 serializer, BIST mode is entered by setting all the input data of the device to a low state. A CLKIN is required for BIST. When the deserializer detects the BIST mode pattern and command (DCA and DCB code), the data and control signal outputs are shut off.

Step 2: Place the DS92LV2422 deserializer in BIST mode by setting BISTEN = H. The deserializer is now in BIST mode and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS pin switches low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate.

Step 3: To stop BIST mode, the deserializer BISTEN pin is set low. The deserializer stops checking the data, and the final test result is held on the PASS pin. If the test ran error free, the PASS output is high. If there was one or more errors detected, the PASS output is low. The PASS output state is held until a new BIST is run, the device is RESET, or powered down. The BIST duration is user controlled by the duration of the BISTEN signal.

Step 4: To return the link to normal operation, the serializer BISTEN input is set low. The Link returns to normal operation.

Figure 33 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error-free, and Case 2 shows one with multiple errors. In most cases, it is difficult to generate errors due to the robustness of the link (differential data transmission and so forth), thus they may be introduced by greatly extending the cable length, faulting the interconnect, or reducing signal condition enhancements (de-emphasis, VODSEL, or Rx equalization).

Figure 32. BIST Mode Flow Diagram

Figure 33. BIST Waveforms

7.3.6 Optional Serial Bus Control

The serializer and deserializer may also be configured by the use of a serial control bus that is I²C protocol-compatible. By default, the I²C Reg 0x00 = 0x00, and all configuration is set by control or strap pins. Writing reg 0x00 = 0x01 enables or allows configuration by registers; this overrides the control or strap pins. Multiple devices may share the serial control bus, because multiple addresses are supported (see Figure 34).

The serial bus is comprised of three pins. The SCL is a serial bus clock input. The SDA is the serial bus data input or output signal. Both SCL and SDA signals require an external pullup resistor to V_DDIO. For most applications, a 4.7-kΩ pullup resistor to V_DDIO may be used. The resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled high or driven low.

Figure 34. Serial Control Bus Connection

The third pin is the ID[X] pin. This pin sets one of four possible device addresses. Two different connections are possible:

• The pin may be pulled to V_DD (1.8 V, not V_DDIO) with a 10-kΩ resistor.
• The pin may be pulled to V_DD (1.8 V, not V_DDIO) with a 10-kΩ resistor and pulled down to ground with a recommended value RID resistor. This creates a voltage divider that sets the other three possible addresses.

See Table 11 for the serializer and Table 12 for the deserializer. Do not tie ID[X] directly to VSS.

The serial bus protocol is controlled by START, START-repeated, and STOP phases. A START occurs when SCL transitions low while SDA is high. A STOP occurs when SDA transition high while SCL is also high (see Figure 35).

Figure 35. START and STOP Conditions

To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't match the slave address of a device, it Not-acknowledges (NACKs) the master by letting SDA be pulled high. ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a start condition or a repeated start condition. All communication on the bus ends with a stop condition. A READ is shown in Figure 36 and a WRITE is shown in Figure 37.

If the serial bus is not required, the three pins may be left open (NC).

Figure 36. Serial Control Bus — READ

Figure 37. Serial Control Bus — WRITE

7.4.1 Serializer and Deserializer Operating Modes and Reverse Compatibility (CONFIG[1:0])

The DS92LV242x chipset is compatible with other single serial lane Channel Link II or FPD-Link II devices. Configuration modes are provided for reverse compatibility with the DS90C241 / DS90C124 chipset (FPD-Link II Generation 1) and also the DS90UR241 / DS90UR124 chipset (FPD-Link II Generation 2) by setting the respective mode with the CONFIG[1:0] pins on the serializer or deserializer as shown in Table 13 and Table 14. This selection also determines whether the control signal filter feature is enabled or disabled in the normal mode. This feature may be controlled by pin or by register.

Table 15. SERIALIZER — Serial Bus Control Registers

Table 16. DESERIALIZER — Serial Bus Control Registers