ZHCSD35B November 2014 – August 2019 DS90UH949-Q1
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | PIN/FREQ. | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|---|
| GPIO FREQUENCY(4) | |||||||
| Rb,FC | Forward Channel GPIO Frequency | Single-Lane, IN_CLK = 25 MHz - 96 MHz | GPIO[3:0], D_GPIO[3:0] | 0.25 × IN_CLK | MHz | ||
| Dual-Lane, IN_CLK/2 = 25 MHz - 85 MHz | 0.125 × IN_CLK | ||||||
| tGPIO,FC | GPIO Pulse Width, Forward Channel | Single-Lane, IN_CLK = 25 MHz - 96 MHz | GPIO[3:0], D_GPIO[3:0] | >2 / IN_CLK | s | ||
| Dual-Lane, IN_CLK/2 = 25 MHz - 85 MHz | >2 / (IN_CLK/2) | ||||||
| TMDS INPUT | |||||||
| Skew-Intra | Maximum Intra-Pair Skew | IN_CLK±, IN_D[2:0]± | 0.4 | UITMDS(1) | |||
| Skew-Inter | Maximum Inter-Pair Skew | 0.2 × Tchar(2) + 1.78 | ns | ||||
| tIJIT | TMDS Clock Input Jitter | Bit Error Rate ≤1E-10 | IN_CLK± | 0.3 | UITMDS(1) | ||
| FPD-LINK III OUTPUT | |||||||
| tLHT | Low Voltage Differential Low-to-High Transition Time | 80 | ps | ||||
| tHLT | Low Voltage Differential High-to-Low Transition Time | 80 | ps | ||||
| tXZD | Output Active to OFF Delay | PDB = L | 100 | ns | |||
| tPLD | Lock Time (HDMI Rx) | 5 | ms | ||||
| tSD | Delay — Latency | IN_CLK± | 145*T(1) | s | |||
| tDJIT | Output Total Jitter (Figure 5 ) | Random Pattern | Single-Lane: High pass filter IN_CLK/20 | 0.3 | UIFPD3(3) | ||
| Dual-lane: High pass filter IN_CLK/40 | |||||||
| λSTXBW | Jitter Transfer Function (-3-dB Bandwidth) | 960 | kHz | ||||
| δSTX | Jitter Transfer Function Peaking | 0.1 | dB | ||||