ZHCSEN8A NOVEMBER 2014 – January 2016 DS90UH940-Q1
PRODUCTION DATA.
This device provides separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description table provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.
When power is applied, power from the highest voltage rail to the lowest voltage rail on any of the supply pins. For 3.3V IO operation, VDDIO and VDD33 can be powered by the same supply and ramped simultaneously. The power supply ramp (VDD12, VDD33, and VDDIO) should be faster than 1.5ms with a monotonic rise. A large capacitor on the PDB pin is needed to ensure PDB arrives after all the supply pins have settled to the recommended operating voltage. When PDB pin is pulled up to VDD33, a 10 kΩ pull-up and a >10 μF capacitor to GND are required to delay the PDB input signal rise. All inputs must not be driven until both VDD33 and VDDIO has reached steady state. Pins VDD33_A and VDD33_B should both be externally connected, bypassed, and driven to the same potential (they are not internally connected).