ZHCSJR7 May 2019 DS90UB949A-Q1
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 DC Electrical Characteristics
- 6.6 AC Electrical Characteristics
- 6.7 DC and AC Serial Control Bus Characteristics
- 6.8 Recommended Timing for the Serial Control Bus
- 6.9 Timing Diagrams
- 6.10 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 High-Definition Multimedia Interface (HDMI)
- 7.3.2 Transition Minimized Differential Signaling
- 7.3.3 Enhanced Display Data Channel
- 7.3.4 Extended Display Identification Data (EDID)
- 7.3.5 Consumer Electronics Control (CEC)
- 7.3.6 +5-V Power Signal
- 7.3.7 Hot Plug Detect (HPD)
- 7.3.8 High-Speed Forward Channel Data Transfer
- 7.3.9 Back Channel Data Transfer
- 7.3.10 FPD-Link III Port Register Access
- 7.3.11 Power Down (PDB)
- 7.3.12 Serial Link Fault Detect
- 7.3.13 Interrupt Pin (INTB)
- 7.3.14 Remote Interrupt Pin (REM_INTB)
- 7.3.15 General-Purpose I/O
- 7.3.16 SPI Communication
- 7.3.17 Backward Compatibility
- 7.3.18 Audio Modes
- 7.3.19 Built-In Self Test (BIST)
- 7.3.20 Internal Pattern Generation
- 7.3.21 Spread-Spectrum Clock Tolerance
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1 Serial Control Bus
- 7.5.2 Multi-Master Arbitration Support
- 7.5.3 I2C Restrictions on Multi-Master Operation
- 7.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
- 7.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
- 7.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
- 7.5.7 Prevention of I2C Faults During Abrupt System Faults
- 7.6 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RGC|64
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RGC|64
訂購信息
8.2.1 Design Requirements
The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme. External AC-coupling capacitors must be placed in series in the FPD-Link III signal path as shown in Figure 28.
Table 13. Design Parameters
| DESIGN PARAMETER | EXAMPLE VALUE |
|---|---|
| VDDIO | 1.8 V |
| STP configuration, AC-coupling capacitor for DOUT0± and DOUT1± with DS90Ux92x-Q1 deserializers.
Note the 92x does not support single-ended coax unless specifically specified. |
100 nF |
| STP/STQ configuration, AC-coupling capacitor for DOUT0± and DOUT1± with DS90Ux94x-Q1 deserializers | 33 nF or 100 nF |
| Coax configuration, AC-coupling capacitor for DOUT0± and DOUT1± with DS90Ux94x-Q1 deserializers | 100 nF on DOUT0/1+; 47nF on DOUT0/1–
or 33 nF on DOUT0/1+; 15nF on DOUT0/1– |
For applications that use a single-ended, 50-Ω coaxial cable, the unused data pins (DOUT0–, DOUT1–) should use a 15-nF capacitor and should be terminated with a 50-Ω resistor.
Figure 28. AC-Coupled Connection (STP) 
Figure 29. AC-Coupled Connection (Coaxial) For high-speed FPD–Link III transmissions, the smallest available package should be used for the AC-coupling capacitor. This will help minimize degradation of signal quality due to package parasitics.