ZHCSD36A November 2014 – March 2019 DS90UB947-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 DC Electrical Characteristics
- 6.6 AC Electrical Characteristics
- 6.7 DC and AC Serial Control Bus Characteristics
- 6.8 Recommended Timing for the Serial Control Bus
- 6.9 Timing Diagrams
- 6.10 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 High-Speed Forward Channel Data Transfer
- 7.3.2 Back Channel Data Transfer
- 7.3.3 FPD-Link III Port Register Access
- 7.3.4 OpenLDI Input Frame and Color Bit Mapping Select
- 7.3.5 Video Control Signals
- 7.3.6 Power Down (PDB)
- 7.3.7 Serial Link Fault Detect
- 7.3.8 Interrupt Pin (INTB)
- 7.3.9 Remote Interrupt Pin (REM_INTB)
- 7.3.10 General-Purpose I/O
- 7.3.11 SPI Communication
- 7.3.12 Backward Compatibility
- 7.3.13 Audio Modes
- 7.3.14 Repeater
- 7.3.15 Built-In Self Test (BIST)
- 7.3.16 Internal Pattern Generation
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1 Serial Control Bus
- 7.5.2 Multi-Master Arbitration Support
- 7.5.3 I2C Restrictions on Multi-Master Operation
- 7.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
- 7.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
- 7.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
- 7.6 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
8.2.1 Design Requirements
The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme. External AC coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in Figure 38.
Table 12. Design Parameters
| DESIGN PARAMETER | EXAMPLE VALUE |
|---|---|
| VDDIO | 1.8 V |
| AC Coupling Capacitor for DOUT0± and DOUT1± with 92x deserializers | 100 nF |
| AC Coupling Capacitor for DOUT0± and DOUT1± with 94x deserializers | 33 nF |
For applications utilizing single-ended 50Ω coaxial cable, the unused data pins (DOUT0-, DOUT1-) should utilize a 15nF capacitor and should be terminated with a 50Ω resistor.
Figure 38. AC-Coupled Connection (STP) 
Figure 39. AC-Coupled Connection (Coaxial) For high-speed FPD–Link III transmissions, the smallest available package should be used for the AC coupling capacitor. This will help minimize degradation of signal quality due to package parasitics.