4 修訂歷史記錄
Changes from A Revision (March 2019) to B Revision
- Changed VDD11 maximum from 1.32 V back to 1.7 VGo
- 添加了接收文檔更新通知 部分Go
Changes from * Revision (November 2014) to A Revision
- Changed all references of HDMI Clock to TMDS Clock.Go
- Changed the VTERM pin descriptionGo
- Changed VDD11 maximum from: 1.7 V to: 1.32 VGo
- Added RX_5V parameter to the Recommended Operating ConditionsGo
- Added TCLH1/2 and TCHL1/2 parameters to the Recommended Operating ConditionsGo
- Changed the TMDS jitter specification in the AC Electrical Characteristics tableGo
- Added information about using I2S with the DS90UH926-Q1 in the Audio Modes sectionGo
- Deleted Auto Soft Sleep mode from the MODE_SEL[1:0] Settings tableGo
- Added Frequency Detection Circuit sectionGo
- Added 5% resistor information to the Serial Control Bus sectionGo
- Added information to Multi-Master Arbitration Support sectionGo
- Added additional information to register 0x01Go
- Added registers 0x00, 0x13, 0x15, 0x5B, 0xC0, 0xC2, 0xC3, 0xC6, 0xC8, 0xCE, and 0xD0 to default listGo
- Changed information about GPIO0 modes x00 and x10Go
- Changed information about GPIO1 modes x00 and x10Go
- Added reset information to register 0x15Go
- Changed the register 0x1A informationGo
- Added Registers 0x40, 0x41, and 0x42Go
- Deleted Rev A1 silicon informationGo
- Added 'Set to 0' test to the 0x5B register descriptionGo
- Changed register 0x5C[4:3] information. Go
- Added Page 0x10 RegisterGo
- Added Page 0x14 RegisterGo
- Changed graph caption from: 1080p60 Video at 2.6 Gbps Serial Line Rate (One of Two Lanes) to: 720p60 Video at 2.6-Gbps Serial Line Rate, Single Lane FPD-Link III OutputGo
- Changed Power-Up Requirements sectionGo