10.3.1 Serial Frame Format

The high-speed forward channel is composed of 28 bits of data containing video data, sync signals, I²C and parity bits. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized, balanced and scrambled. The 28-bit frame structure changes in the 12-bit low-frequency mode, 12-bit high frequency mode and the 10-bit mode internally and is seamless to the customer. The bidirectional control channel data is transferred over the single serial link along with the high-speed forward data. This architecture provides a full duplex low-speed forward and backward path across the serial link together with a high-speed forward channel without the dependence on the video blanking phase.

10.3.2 Line Rate Calculations for the DS90UB91xQ

The DS90UB913Q-Q1 device divides the clock internally by divide-by-1 in the 12-bit low-frequency mode, by divide-by-2 in the 10-bit mode and by divide-by-1.5 in the 12-bit high-frequency mode. Conversely, the DS90UB914Q-Q1 multiplies the recovered serial clock to generate the proper pixel clock output frequency. Thus the maximum line rate in the three different modes remains 1.4 Gbps. The following are the formulae used to calculate the maximum line rate in the different modes.

• For 12-bit low-frequency mode, Line rate = f_PCLK × 28; that is, f_PCLK= 50 MHz, line rate = 50 × 28 = 1.4 Gbps
• For 10-bit mode, Line rate = f_PCLK / 2 × 28; that is, f_PCLK= 100 MHz, line rate = (100 / 2) × 28 = 1.4 Gbps
• For the 12-bit high-frequency mode, Line rate = f_PCLK × (2 / 3) × 28; that is, f_PCLK= 75 MHz, line rate = (75) × (2 / 3) × 28 = 1.4 Gbps

10.3.3 Deserializer Multiplexer Input

The DS90UB914Q-Q1 offers a 2:1 multiplexer that can be used to select which camera is used as the input. Figure 25 shows the operation of the 2:1 multiplexer in the deserializer. The selection of the camera can be pin controlled as well as register controlled. Both the deserializer inputs cannot be enabled at the same time. If the Serializer A is selected as the active serializer, the back-channel for Deserializer A turns ON and vice versa. To switch between the two cameras, first the Serializer B has to be selected using the SEL pin/register on the deserializer. After that the back channel driver for Deserializer B has to be enabled using the register in the deserializer.

Figure 25. Using the Multiplexer on the Deserializer to Enable a Two-Camera System

10.3.4 Error Detection

The chipset provides error detection operations for validating data integrity in long distance transmission and reception. The data error detection function offers users flexibility and usability of performing bit-by-bit data transmission error checking. The error detection operating modes support data validation of the following signals:

• Bidirectional control channel data across the serial link
• Parallel video/sync data across the serial link

The chipset provides one parity bit on the forward channel and 4 CRC bits on the back channel for error detection purposes. The DS90UB91xQ-Q1 chipset checks the forward and back channel serial links for errors and stores the number of detected errors in two 8-bit registers in the serializer and the deserializer respectively.

To check parity errors on the forward-channel, monitor registers 0x1A and 0x1B on the deserializer. If there is a loss of LOCK, then the counters on registers 0x1A and 0x1B are reset.

To check CRC errors on the back-channel, monitor registers 0x0A and 0x0B on the serializer.

10.3.5 Description of Bidirectional Control Bus and I²C Modes

The I²C-compatible interface allows programming of the DS90UB913Q-Q1, DS90UB914Q-Q1, or an external remote device (such as image sensor) through the bidirectional control channel. Register programming transactions to/from the DS90UB913xQ-Q1 chipset are employed through the clock (SCL) and data (SDA) lines. These two signals have open-drain I/Os and both lines must be pulled up to VDDIO by an external resistor. Pullup resistors or current sources are required on the SCL and SDA busses to pull them high when they are not being driven low. A logic LOW is transmitted by driving the output low. Logic HIGH is transmitted by releasing the output and allowing it to be pulled up externally. The appropriate pullup resistor values will depend upon the total bus capacitance and operating speed. The DS90UB91xQ-Q1 I²C bus data rate supports up to 400 kbps according to I²C fast mode specifications.

Figure 26. Write Byte

Figure 27. Read Byte

Figure 28. Basic Operation

Figure 29. Start and Stop Conditions

10.3.6 Slave Clock Stretching

The I²C-compatible interface allows programming of the DS90UB913Q-Q1, DS90UB914Q-Q1, or an external remote device (such as image sensor) through the bidirectional control.

The slave device will not control the clock and only stretches it until the remote peripheral has responded. The I²C master must support clock stretching to operate with the DS90UB91xQ-Q1 chipset.

10.3.7 I²C Pass-Through

I²C pass-through provides an alternative means to independently address slave devices. The mode enables or disables I²C bidirectional control channel communication to the remote I²C bus. This option is used to determine whether or not an I²C instruction is to be transferred over to the remote I²C device. When enabled, the I²C bus traffic will continue to pass through, I²C commands will be excluded to the remote I²C device. The pass-through function also provides access and communication to only specific devices on the remote bus.

See Figure 30 for an example of this function.

If master controller transmits I²C transaction for address 0xA0, the SER A with I²C pass-through enabled will transfer I²C commands to remote Camera A. The SER B with I²C pass-through disabled, any I²C commands will be bypassed on the I²C bus to Camera B.

Figure 30. I²C Pass-Through

10.3.8 ID[x] Address Decoder on the Serializer

The ID[x] pin on the serializer is used to decode and set the physical slave address of the serializer (I²C only) to allow up to five devices on the bus connected to the serializer using only a single pin. The pin sets one of the 5 possible addresses for each serializer device. The pin must be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩ resistor and a pulldown resistor (RID) of the recommended value to set the physical device address. The recommended maximum resistor tolerance is 1%.

Figure 31. ID[x] Address Decoder on the Serializer

10.3.9 ID[x] Address Decoder on the Deserializer

The IDx[0] and IDx[1] pins on the deserializer are used to decode and set the physical slave address of the deserializer (I²C only) to allow up to 16 devices on the bus using only two pins. The pins set one of 16 possible addresses for each deserializer device. As there will be more deserializer devices connected on the same board than serializers, more I²C device addresses have been defined for the DS90UB914Q-Q1 deserializer than the DSDS90UB913Q-Q1 serializer. The pins must be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩ resistor and two pulldown resistors (RID0 and RID1) of the recommended value to set the physical device address. The recommended maximum resistor tolerance is 1%.

Figure 32. ID[x[ Address Decoder on the Deserializer

10.3.10 Programmable Controller

An integrated I²C slave controller is embedded in the DS90UB913Q-Q1 serializer as well as the DS90UB914Q-Q1 deserializer. It must be used to configure the extra features embedded within the programmable registers or it can be used to control the set of programmable GPIOs.

10.3.11 Synchronizing Multiple Cameras

For applications requiring multiple cameras for frame-synchronization, TI recommends to utilize the General-Purpose Input/Output (GPIO) pins to transmit control signals to synchronize multiple cameras together. To synchronize the cameras properly, the system controller needs to provide a field sync output (such as a vertical or frame sync signal) and the cameras must be set to accept an auxiliary sync input. The vertical synchronize signal corresponds to the start and end of a frame and the start and end of a field.

See Figure 33 for an example of synchronizing multiple cameras.

The maximum time (t1) between the rising edge of GPIO (that is, sync signal) arriving at Camera A and Camera B is 25 µs.

Figure 33. Synchronizing Multiple Cameras

Figure 34. GPIO Delta Latency

10.3.12 General-Purpose I/O (GPIO) Descriptions

There are 4 GPOs on the serializer and 4 GPIOs on the deserializer when the DS90UB91xQ-Q1 chipsets are run off the pixel clock from the imager as the reference clock source. The GPOs on the serializer can be configured as outputs for the input signals that are fed into the deserializer GPIOs. In addition, the GPOs on the serializer can behave as outputs of the local register on the serializer. The GPIOs on the deserializer can be configured to be the input signals feeding the output of the GPOs on the serializer. In addition the GPIOs on the deserializer can be configured to behave as outputs of the local register on the deserializer. If the DS90UB91xQ-Q1 chipsets are run off the external oscillator source as the reference clock, then GPO3 on the serializer is automatically configured to be the input for the external clock and GPIO2 on the deserializer is configured to be the output of the divide-by-2 clock which is fed into the imager as its reference clock. In this case, the GPIO2 and GPIO3 on the deserializer can only behave as outputs of the local register on the deserializer. The GPIO maximum switching rate is up to 66 kHz when configured for communication between deserializer GPIO to serializer GPO.

10.3.13 LVCMOS VDDIO Option

1.8-V, 2.8-V, and 3.3-V serializer inputs and 1.8-V and 3.3-V deserializer outputs are user configurable to provide compatibility with 1.8-V, 2.8-V and 3.3-V system interfaces.

10.3.14 Deserializer – Adaptive Input Equalization (AEQ)

The receiver inputs provide an adaptive input equalization filter in order to compensate for loss from the media. The level of equalization can also be manually selected through register controls. The fully-adaptive equalizer output can be seen using the CMLOUTP/CMLOUTN pins in the deserializer.

Figure 35. Maximum Equalizer Gain vs. Line Frequency

10.3.15 EMI Reduction

10.4.1 DS90UB91xQ-Q1 Operation With External Oscillator as Reference Clock

In some applications, the pixel clock that comes from the imager can have jitter which exceeds the tolerance of the DS90UB91xQ-Q1 chipsets. In this case, the DS90UB913Q-Q1 device should be operated by using an external clock source as the reference clock for the DS90UB91xQ-Q1 chipsets. This is the recommended operating mode. The external oscillator clock output goes through a divide-by-2 circuit in the DS90UB913Q-Q1 serializer and this divided clock output is used as the reference clock for the imager. The output data and pixel clock from the imager are then fed into the DS90UB913Q-Q1 device. Figure 36 shows the operation of the DS90UB1xQ-Q1 chipsets while using an external automotive grade oscillator.

Figure 36. DS90UB91xQ-Q1 Operation in the External Oscillator Mode

When the DS90UB913Q-Q1 device is operated using an external oscillator, the GPO3 pin on the
DS90UB913Q-Q1 is the input pin for the external oscillator. In applications where the DS90UB913Q-Q1 device is operated from an external oscillator, the divide-by-2 circuit in the DS90UB913Q-Q1 device feeds back the divided clock output to the imager device through GPO2 pin. The pixel clock to external oscillator ratios needs to be fixed for the 12-bit high-frequency mode and the 10-bit mode.

For example, if the external oscillator frequency is 48 MHz in the 10-bit mode, the pixel clock frequency of the imager needs to be twice of the external oscillator frequency, that is, 96 MHz. If the external oscillator frequency is 48 MHz in the 12-bit high-frequency mode, the pixel clock frequency of the imager needs to be 1.5 times of the external oscillator frequency, that is, 72 MHz. In this mode, GPO2 and GPO3 on the serializer cannot act as the output of the input signal coming from GPIO2 or GPIO3 on the deserializer.

10.4.2 DS90UB91xQ-Q1 Operation With Pixel Clock from Imager as Reference Clock

The DS90UB91xQ-Q1 chipsets can be operated by using the pixel clock from the imager as the reference clock.Figure 37 shows the operation of the DS90UB91xQ-Q1 chipsets using the pixel clock from the imager. If the DS90UB913Q-Q1 device is operated using the pixel clock from the imager as the reference clock, then the imager uses an external oscillator as its reference clock. There are 4 GPIOs on the serializer and 4 GPIOs on the deserializer in this mode.

Figure 37. DS90UB91xQ-Q1 Operation in PCLK mode

10.4.3 MODE Pin on Serializer

The mode pin on the serializer can be configured to select if the DS90UB913Q-Q1 device is to be operated from the external oscillator or the PCLK from the imager. The pin must be pulled to V_DD (1.8 V, not V_DDIO) with a
10-kΩ resistor and a pulldown resistor (R_MODE) of the recommended value to set the modes shown in Figure 38. The recommended maximum resistor tolerance is 1%.

Figure 38. MODE Pin Configuration on DS90UB913Q-Q1

10.4.4 MODE Pin on Deserializer

The mode pin on the deserializer can be used to configure the device to work in the 12-bit low-frequency mode, 12-bit high frequency mode or the 10-bit mode of operation. Internally, the DS90UB91xQ-Q1 chipset operates in a divide-by-1 mode in the 12-bit low-frequency mode, divide-by-2 mode in the 10-bit mode and a divide-by-1.5 mode in the 12-bit high-frequency mode. The pin must be pulled to V_DD (1.8 V, not V_DDIO) with a 10-kΩ resistor and a pulldown resistor (R_MODE) of the recommended value to set the different modes in the deserializer as mentioned in Table 4. The deserializer automatically configures the serializer to correct mode through the back-channel. The recommended maximum resistor tolerance is 1%

.

Figure 39. Mode Pin Configuration on DS90UB914Q-Q1 Deserializer

10.4.5 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)

When PDB is driven HIGH, the CDR PLL of the deserializer begins locking to the serial input and LOCK is TRI-STATE or LOW (depending on the value of the OEN setting). After the DS90UB914Q-Q1 completes its lock sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is available on the parallel bus and PCLK outputs. The states of the outputs are based on the OEN and OSS_SEL setting (Table 3). See Figure 20.

10.4.6 Multiple Device Addressing

Some applications require multiple camera devices with the same fixed address to be accessed on the same I²C bus. The DS90UB91xQ-Q1 provides slave ID matching/aliasing to generate different target slave addresses when connecting more than two identical devices together on the same bus. This allows the slave devices to be independently addressed. Each device connected to the bus is addressable through a unique ID by programming of the SLAVE_ID_MATCH register on deserializer. This will remap the SLAVE_ID_MATCH address to the target SLAVE_ID_INDEX address; up to 8 ID indexes are supported. The ECU Controller must keep track of the list of I²C peripherals in order to properly address the target device.

See Figure 40 for an example of multiple device addressing.

• ECU is the I²C master and has an I²C master interface
• The I²C interfaces in DES A and DES B are both slave interfaces
• The I²C protocol is bridged from DES A to SER A and from DES B to SER B
• The I²C interfaces in SER A and SER B are both master interfaces

If master controller transmits I²C slave 0xA0, the DES A address 0xC0 will forward the transaction to remote Camera A. If the controller transmits slave address 0xA4, the DES B 0xC2 will recognize that 0xA4 is mapped to 0xA0 and will be transmitted to the remote Camera B. If controller sends command to address 0xA6, the DES B 0xC2 will forward transaction to slave device 0xA2.

The Slave ID index/match is supported only in the camera mode (SER: MODE pin = L; DES: MODE pin = H). For Multiple device addressing in display mode (SER: MODE pin = H; DES: MODE pin = L), use the I²C pass-through function.

Figure 40. Multiple Device Addressing

10.4.7 Powerdown

The SER has a PDB input pin to ENABLE or Powerdown (SLEEP) the device. The modes can be controlled by the host and is used to disable the Link to save power when the remote device is not operational. In this mode, if the PDB pin is tied High and the SER will enter SLEEP when the PCLK stops. When the PCLK starts again, the SER will then lock to the valid input PCLK and transmit the data to the DES. In SLEEP mode, the high-speed driver outputs are static (High). The DES has a PDB input pin to ENABLE or Powerdown (SLEEP) the device. This pin can be controlled by the system and is used to disable the DES to save power. An auto mode is also available. In this mode, the PDB pin is tied High and the DES will enter SLEEP when the serial stream stops. When the serial stream starts up again, the DES will lock to the input stream and assert the LOCK pin and output valid data. In SLEEP mode, the Data and PCLK outputs are set by the OSS_SEL configuration.

10.4.8 Pixel Clock Edge Select (TRFB / RRFB)

The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0, data is strobed on the falling edge of the PCLK.

Figure 41. Programmable PCLK Strobe Select

10.4.9 Power-Up Requirements and PDB Pin

When power is applied, the VDDIO supply needs to reach the expected operating voltage (1.8 V to 3.3 V) before the other supplies (VDDn) begin to ramp. It is required to delay and release the PDB Signal after VDD (VDDn and VDDIO) power supplies have settled to the recommended operating voltage. An external RC network can be connected to the PDB pin to ensure PDB arrives after all the VDD has stabilized.

Figure 42. Power-Up Sequencing

10.4.10 Built-In Self Test

An optional AT-Speed, Built-In Self Test (BIST) feature supports the testing of the high-speed serial link and low-speed back channel. This is useful in the prototype stage, equipment production, and in-system test and also for system diagnostics.

10.4.11 BIST Configuration and Status

The chipset can be programmed into BIST mode using either pins or registers. By default BIST configuration is controlled through pins. BIST can be configured through registers using BIST Control register (0x24). Pin based configuration is defined as follows:

• BISTEN : Enable the BIST Process
• GPIO0 and GPIO1 : Defines the BIST clock source (PCLK vs. various frequencies of internal OSC

The BIST mode provides various options for source PCLK. Using external pins, GPIO0 and GPIO1 or using registers, customer can program the BIST mode to use external PCLK or various OSC frequencies. The BIST status can be monitored real time on PASS pin. For every frame with error(s), PASS pin toggles low for half PCLK period. If two consecutive frames have errors, PCLK will toggle twice to allow counting of frames with errors. Once the BIST is done, the PASS pin reflects the pass/fail status of the last BIST run. The status can also be read through I²C for the number of frames in errors. BIST status on PASS pin remains until it is changed by a new BIST session or a reset. The BIST status on PASS pin is not maintained till RX loses LOCK after BISTEN is deassserted. To evaluate BIST in the external oscillator mode, both external oscillator and PCLK need to be present.

The BIST status on PASS pin is not maintained till RX loses LOCK after BISTEN is deassserted. So for all practical purposes, the BIST status can be monitored from register 0x25, that is, BIST Error Count on the DS90UB914Q-Q1 deserializer. To evaluate BIST in the external oscillator mode, both external oscillator and PCLK need to be present.

10.4.11.1 Sample BIST Sequence

Step 1. For the DS90UB91xQ-Q1 FPD-Link III chipset, BIST Mode is enabled through the BISTEN pin of DS90UB914Q-Q1 FPD-Link III deserializer. The desired clock source is selected through the GPIO0 and GPIO1 pins as shown in Table 4.

Step 2. The DS90UB913Q-Q1 serializer is woken up through the back channel if it is not already on. The SSO pattern on the data pins is send through the FPD-Link III to the deserializer. Once the serializer and deserializer are in the BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST starts checking data stream. If an error in the payload is detected the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate.

Step 3. To stop the BIST mode, the deserializer BISTEN pin is set low. The deserializer stops checking the data. The final test result is not maintained on the PASS pin. To monitor the BIST status, check the BIST Error Count register, 0x25 on the deserializer.

Step 4. The link returns to normal operation after the deserailzer BISTEN pin is low. Figure 44 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases, it is difficult to generate errors due to the robustness of the link (differential data transmission, and so forth), thus they may be introduced by greatly extending the cable length, faulting the interconnect, or by reducing signal condition enhancements (RX equalization).

Figure 43. AT-Speed BIST System Flow Diagram

Figure 44. BIST Timing Diagram

Table 7. DS90UB913Q-Q1 Control Registers

Table 8. DS90UB914Q-Q1 Control Registers

Table 9. Clock Sources for Forward Channel Frame on the Serializer During Normal Operation

Table 10. BIST Clock Sources