SNLS344G July 2011 – August 2015 DS80PCI102
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
5 Pin Configuration and Functions
RTW Package
24 Pins
Top View
Pin Functions(1)(2)(3)(4)
| PIN | I/O, TYPE | DESCRIPTION | |||
|---|---|---|---|---|---|
| NAME | NO. | ||||
| DIFFERENTIAL HIGH SPEED I/O'S | |||||
| INA+, INA-, INB+, INB- |
24, 23 11, 12 |
I, CML | Inverting and noninverting differential inputs to the equalizer. A gated on-chip 50-Ω termination resistor connects INn+ to VDD and INn- to VDD depending on the state of RXDET. See Table 4
AC coupling required on high-speed I/O |
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| OUTA+, OUTA-, OUTB+, OUTB- |
7, 8 20, 19 |
O, CML | Inverting and noninverting 50-Ω driver outputs with de-emphasis. Compatible with AC-coupled CML inputs. | ||
| CONTROL PINS — SHARED (LVCMOS) | |||||
| ENSMB | 3 | I, 4-LEVEL, LVCMOS | System management bus (SMBus) enable pin Tie 1 kΩ to VDD (2.5-V mode) or VIN (3.3-V mode) = Register access SMBus slave mode FLOAT = Read external EEPROM (master SMBUS mode) Tie 1 kΩ to GND = Pin mode |
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| ENSMB = 1 (SMBus SLAVE MODE) | |||||
| SCL | 5 | I, 2-LEVEL, LVCMOS, O, open drain | In SMBus Slave Mode, this pin is the SMBus clock I/O. Clock input or open drain output. External 2-kΩ to 5-kΩ pullup resistor to VDD or VIN recommended as per SMBus interface standards.(5) |
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| SDA | 4 | I, 2-LEVEL, LVCMOS, O, open drain | In both SMBus Modes, this pin is the SMBus data I/O. Data input or open drain output. External 2-kΩ to 5-kΩ pullup resistor to VDD or VIN recommended as per SMBus interface standards.(5) |
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| AD0-AD3 | 10, 9, 2, 1 | I, 4-LEVEL, LVCMOS | SMBus Slave Address Inputs. In both SMBus Modes, these pins are the user set SMBus slave address inputs. External 1-kΩ pullup or pulldown recommended. |
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| READEN | 17 | I, 2-LEVEL, LVCMOS | When in SMBus Slave Mode the READEN pin must be tied LOW for the AD[3:0] to be active. If this pin is tied HIGH or FLOAT, the device slave address is 0xB0. | ||
| ENSMB = FLOAT (SMBus MASTER MODE) | |||||
| SCL | 5 | I, 2-LEVEL, LVCMOS, O, open drain | Clock output when loading EEPROM configuration, reverting to SMBus clock input when EEPROM load is complete (DONE = 0). External 2-kΩ to 5-kΩ pullup resistor to VDD or VIN recommended as per SMBus interface standards.(5) |
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| SDA | 4 | I, 2-LEVEL, LVCMOS, O, open drain | In both SMBus Modes, this pin is the SMBus data I/O. Data input or open drain output. External 2-kΩ to 5-kΩ pullup resistor to VDD or VIN recommended as per SMBus interface standards.(5) |
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| AD0-AD3 | 10, 9, 2, 1 | I, 4-LEVEL, LVCMOS | SMBus Slave Address Inputs. In both SMBus Modes, these pins are the user set SMBus slave address inputs. External 1-kΩ pullup or pulldown recommended. |
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| READEN | 17 | I, 2-LEVEL, LVCMOS | A logic low on this pin starts the load from the external EEPROM.(6)
Once EEPROM load is complete (DONE = 0), this pin functionality remains as READEN. It does not revert to an SD_TH input. |
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| DONE | 18 | O, 2-LEVEL, LVCMOS | Valid register load status output HIGH = External EEPROM load failed or incomplete LOW = External EEPROM load passed |
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| ENSMB = 0 (PIN MODE) | |||||
| EQA0, EQA1 EQB0, EQB1 |
10, 9 1, 2 |
I, 4-LEVEL, LVCMOS | EQA[1:0] and EQB[1:0] control the level of equalization on the input pins. The pins are active only when ENSMB is deasserted (LOW). When ENSMB goes high the SMBus registers provide independent control of each lane, and the EQA[1:0] and EQB[1:0] pins are converted to SMBUS AD[3:0] inputs. See Table 2. |
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| DEMA, DEMB | 4, 5 | I, 4-LEVEL, LVCMOS | DEMA DEMB controls the level of de-emphasis. The DEMA/B pins are only active when ENSMB is deasserted (LOW). DEMA controls the A channel and DEMB controls the B channel. When ENSMB goes high the SMBus registers provide independent control of each channel and the DEM pins are converted to SMBUS SDA and SCL pins. See Table 3. |
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| CONTROL PINS — BOTH PIN AND SMBUS MODES (LVCMOS) | |||||
| PRSNT | 6 | I, 2-LEVEL, LVCMOS | Cable Present Detect input. High when a cable is not present per PCIe Cabling Spec. 1.0. Puts part into low power mode. When LOW (normal operation) part is enabled. See Table 4. |
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| VOD_SEL | 17 | I, 4-LEVEL, LVCMOS | VOD Select pin. See Table 3. | ||
| VDD_SEL | 16 | I, LVCMOS | Controls the internal regulator. FLOAT = 2.5-V mode Tie GND = 3.3-V mode See Figure 16. |
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| RXDET | 18 | I, 4-LEVEL, LVCMOS | The RXDET pin controls the receiver detect function. Depending on the input level, a 50-Ω or > 50-kΩ termination to the power rail is enabled. See Table 4. |
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| RATE | 13 | I, 4-LEVEL, LVCMOS | RATE control pin selects GEN 1,2 and GEN 3 operating modes. Tie 1 kΩ to GND = GEN 1,2 FLOAT = AUTO Rate Select of Gen1/2 and Gen3 with de-emphasis Tie 20 kΩ to GND = GEN 3 without de-emphasis Tied 1 kΩ to VDD = RESERVED |
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| SD_TH | 14 | I, 4-LEVEL, LVCMOS | Controls the internal Signal Detect Threshold. See Table 5. |
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| POWER | |||||
| VIN | 15 | Power | In 3.3-V mode, feed 3.3 V to VIN In 2.5-V mode, leave floating |
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| VDD | 21, 22 | Power | Power supply pins 2.5-V mode, connect to 2.5-V supply 3.3-V mode, connect 0.1-µF capacitor to each VDD pin (output of LDO) |
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| GND | DAP | Power | Ground pad (DAP - die attach pad). | ||
(1) LVCMOS inputs without the “FLOAT” conditions must be driven to a logic low or high at all times or operation is not verified.
(2) Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10% to 90%.
(3) For 3.3-V mode operation, VIN pin = 3.3 V and the VDD for the 4-level input is 3.3 V.
(4) For 2.5-V mode operation, VDD pin = 2.5 V and the VDD for the 4-level input is 2.5 V.
(5) SCL and SDA pins can be tied either to 3.3 V or 2.5 V, regardless of whether the device is operating in 2.5-V mode or 3.3-V mode.
(6) When READEN is asserted low, the device attempts to load EEPROM. If EEPROM cannot be loaded successfully, for example due to an invalid or blank hex file, the DS80PCI102 waits indefinitely in an unknown state where SMBus access is not possible. DONE pin remains high in this situation.