ZHCSKG1C November 2015 – October 2019 DS280BR810
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
5 Pin Configuration and Functions
ZBF Package
135-Pin nfBGA
Top View
Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| HIGH SPEED DIFFERENTIAL I/O | |||
| RX0N | B15 | Input | Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors assembled on the package substrate. |
| RX0P | C15 | Input | |
| RX1N | A13 | Input | Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors assembled on the package substrate. |
| RX1P | B13 | Input | |
| RX2N | A11 | Input | Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors assembled on the package substrate. |
| RX2P | B11 | Input | |
| RX3N | A9 | Input | Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors assembled on the package substrate. |
| RX3P | B9 | Input | |
| RX4N | A7 | Input | Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors assembled on the package substrate. |
| RX4P | B7 | Input | |
| RX5N | A5 | Input | Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors assembled on the package substrate. |
| RX5P | B5 | Input | |
| RX6N | A3 | Input | Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors assembled on the package substrate. |
| RX6P | B3 | Input | |
| RX7N | B1 | Input | Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors assembled on the package substrate. |
| RX7P | C1 | Input | |
| TX0N | H15 | Output | Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. These outputs are AC coupled with 220-nF capacitors assembled on the package substrate. |
| TX0P | G15 | Output | |
| TX1N | J13 | Output | Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. These outputs are AC coupled with 220-nF capacitors assembled on the package substrate. |
| TX1P | H13 | Output | |
| TX2N | J11 | Output | Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. These outputs are AC coupled with 220-nF capacitors assembled on the package substrate. |
| TX2P | H11 | Output | |
| TX3N | J9 | Output | Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. These outputs are AC coupled with 220-nF capacitors assembled on the package substrate. |
| TX3P | H9 | Output | |
| TX4N | J7 | Output | Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. These outputs are AC coupled with 220-nF capacitors assembled on the package substrate. |
| TX4P | H7 | Output | |
| TX5N | J5 | Output | Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. These outputs are AC coupled with 220-nF capacitors assembled on the package substrate. |
| TX5P | H5 | Output | |
| TX6N | J3 | Output | Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. These outputs are AC coupled with 220-nF capacitors assembled on the package substrate. |
| TX6P | H3 | Output | |
| TX7N | H1 | Output | Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. These outputs are AC coupled with 220-nF capacitors assembled on the package substrate. |
| TX7P | G1 | Output | |
| CALIBRATION CLOCK PINS (FOR SUPPORTING UPGRADE PATH TO PIN-COMPATIBLE RETIMER DEVICE) | |||
| CAL_CLK_IN | E1 | Input | 25-MHz (±100 PPM) 2.5-V single-ended clock from external oscillator. No stringent phase noise or jitter requirements on this clock. A 25-MHz input clock is only required if there is a need to support a future upgrade to the pin-compatible Retimer device. If there is no need to support a future upgrade to a pin-compatible Retimer device, then a 25-MHz clock is not required. this pin can be left floating. This input pin has a weak active pull down and can be left floating if the CAL_CLK feature is not required. |
| CAL_CLK_OUT | E15 | Output | 2.5-V buffered replica of calibration clock input (pin E1) for connecting multiple devices in a daisy-chained fashion. |
| SYSTEM MANAGEMENT BUS (SMBus) PINS | |||
| ADDR0 | D13 | Input, 4-Level | 4-level strap pins used to set the SMBus address of the device. The pin state is read on power-up. The multi-level nature of these pins allows for 16 unique device addresses. The four strap options include:
0: 1 kΩ to GND R: 10 kΩ to GND F: Float 1: 1 kΩ to VDD |
| ADDR1 | E13 | Input, 4-Level | |
| ALL_DONE_N | D3 | Output, LVCMOS | Indicates the completion of a valid EEPROM register load operation when in SMBus master mode (EN_SMB = Float):
High = External EEPROM load failed or incomplete. Low = External EEPROM load successful and complete. When in SMBus slave mode (EN_SMB = 1), this output will be high-Z until READ_EN_N is driven low, at which point ALL_DONE_N will be driven low. This behavior allows the reset signal connected to READ_EN_N of one device to propagate to the subsequent devices when ALL_DONE_N is connected to READ_EN_N in an SMBus slave mode application. |
| EN_SMB | E3 | Input, 4-Level | 4-level 2.5 V input used to select between SMBus master mode (float) and SMBus slave mode (high). The four defined levels are:
0: 1 kΩ to GND - RESERVED R: 10 kΩ to GND - RESERVED F: Float - SMBus master mode 1: 1 kΩ to VDD - SMBus slave mode |
| READ_EN_N | F13 | Input, LVCMOS | Pin has weak pull-up.
This pin is 3.3 V tolerant. SMBus master mode (EN_SMB = Float): When asserted low, initiates the SMBus master mode EEPROM read function. Once EEPROM read is complete (indicated by assertion of ALL_DONE_N low), this pin can be held low for normal device operation. SMBus slave mode (EN_SMB = 1): When asserted low, this causes the device to be held in reset (SMBus state machine reset and register reset). This pin should be pulled high or left floating for normal operation in SMBus slave mode. |
| SDA | E12 | I/O, 3.3-V LVCMOS, Open Drain | SMBus data input or open drain output. External 2 -Ω to 5-kΩ pull-up resistor is required. This pin is 3.3-V LVCMOS tolerant. |
| SDC | F12 | I/O, 3.3-V LVCMOS, Open Drain | SMBus clock input or open drain clock output. External 2-kΩ to 5-kΩ pull-up resistor is required. This pin is 3.3-V LVCMOS tolerant. |
| MISCELLANEOUS PINS | |||
| INT_N | F3 | No Connect | No connect on package. For applications using multiple repeaters and retimers, this pin should be connected to other devices’ INT_N pins. This is only a recommendation for cases where there is a need to support a potential future upgrade to the pin-compatible retimer device, which uses this pin as an interrupt signal to a system controller. |
| TEST0 | E2 | Input, LVCMOS | Reserved test pin. During normal (non-test-mode) operation, this pin is configured as an input and therefore is not affected by the presence of a signal. This pin may be left floating, tied to GND, or connected to a 2.5-V (max) output. |
| TEST1 | E14 | Input, LVCMOS | |
| POWER | |||
| GND | A1, A2, A4, A6, A8, A10, A12, A14, A15, B2, B4, B6, B8, B10, B12, B14, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, D1, D2, D4, D5, D7, D9, D11, D12, D14, D15, E4, E11, F1, F2, F4, F5, F7, F9, F11, F14, F15, G2, G3, G4, G5, G6, G7, G8, G9, G10, G11, G12, G13, G14, H2, H4, H6, H8, H10, H12, H14, J1, J2, J4, J6, J8, J10, J12, J14, J15 | Power | Ground reference. The GND pins on this device should be connected through a low-impedance path to the board GND plane. |
| VDD | D6, D8, D10, E5, E6, E7, E8, E9, E10, F6, F8, F10 | Power | Power supply, VDD = 2.5 V ±5%. Use at least six de-coupling capacitors between the Repeater’s VDD plane and GND as close to the Repeater as possible. For example, four 0.1-μF capacitors and two 1-μF capacitors directly beneath the device or as close to the VDD pins as possible. The VDD pins on this device should be connected through a low-resistance path to the board VDD plane. For more information, see Power Supply Recommendations. |