7.3.1.1 Input Channel Equalization

Physical transmission media comprising traces on printed circuit boards (PCBs) or copper cables exhibit a low-pass frequency response characteristic. The magnitude of the high frequency loss varies with the length of the transmission medium and with the loss of the materials which comprise it. This differential high frequency loss and the frequency-dependent group delay of the transmission medium introduce inter-symbol interference in the high-speed broadband signals propagating through the transmission medium.

To make configuration of these settings easier, the DS110DF111 is designed to determine the correct settings for the CTLE autonomously by automatically adapting these equalizations to the input transmission medium. The automatic adaptation takes place when a signal is first detected at the input to the DS110DF111, immediately after the DS110DF111 acquires phase lock.

The automatic adaptation is also triggered whenever the CDR circuitry is reset. The DS110DF111 uses its internal eye monitor to generate a figure of merit for the adaptation. The DS110DF111 adjusts its CTLE boost settings in a systematic way to optimize this figure of merit. When 8b/10b encoding is used and the input channels has more than 15 dB of loss, the CTLE table and or adaption algorithm needs to be modified so as to prevent CTLE mal-adaption. This scenario occurs when the CTLE boost is insufficient at lower settings to cause regeneration of the high-frequency content of the K28.5 pattern. As boost is increased, the adaption Figure of Merit (FOM) temporarily observes eye closure as the EQ boost begins to restore the high-frequency content. If the FOM does not improve within the look-beyond counter depth, the CTLE will settle at a lower boost, which is insufficient to equalize the signal and provide good BER.

The 5-tap DFE discriminates against input noise and random jitter as well as against crosstalk at the input to the DS110DF111. The DFE tap weights and polarities are adaptive and operate in conjunction with the CTLE to achieve an acceptable BER with more severe channel impairments.

7.3.1.2 Clock And Data Recovery

The DS110DF111 performs its clock and data recovery function by detecting the bit transitions in the incoming data stream and locking its internal VCO to the clock represented by the mean arrival times of these bit transitions. This process produces a recovered clock with greatly reduced jitter at jitter frequencies outside the bandwidth of the CDR Phase-Locked Loop (PLL). This is the primary benefit of using the DS110DF111 in a system. It significantly reduces the jitter present in the data stream, in effect resetting the jitter budget for the system.

7.3.1.3 PRBS Pattern Generator

Each channel in the DS110DF111 can be configured to generate and output its own pseudo random bit sequence (PRBS). The DS110DF111 pattern generators support the following PRBS sequences:

• PRBS-9, 2⁹ - 1
• PRBS-31, 2³¹ - 1

7.3.1.4 Datapath Multiplexer and Output Driver

The DS110DF111 datapath multiplexer is used to control which internal signal will be presented to the output driver block. Inputs to this multiplexer include raw equalized data without clock recovery, retimed data, PRBS patterns, and Loopback data from the other datapath.

The DS110DF111 output driver is used to control specific signal characteristics to enhance transmission quality. The output driver is used to control the following signal features

• Amplitude
• De-Emphasis
• Edge Rate
• Polarity

The DS110DF111 is commonly used in applications where lossy transmission media exist both at the input and the output of the DS110DF111. The CTLE compensates for lossy transmission media at the input to the DS110DF111. The output de-emphasis compensates for the lossy transmission medium at the output of the DS110DF111.

When there is a transition in the output data stream, the output differential voltage reaches its configured maximum value within the configured rise/fall time of the output driver. Following this, the differential voltage rapidly falls off until it reaches the configured VOD level minus the configured de-emphasis level. This accentuates the high-frequency components of the output driver signal at the expense of the low frequency components. The pre-distorted DS110DF111 output signal, with high-frequency components emphasized relative to its low frequency components, exhibits less inter-symbol interference after traveling down a dispersive transmission medium than an undistorted output signal.

An idealized transmit waveform with analog de-emphasis applied is shown in Figure 7.

The output driver is capable of driving variable output voltages with variable amounts of analog de-emphasis. The output voltage and de-emphasis level can be configured by writing registers over the SMBus. The DS110DF111 cannot determine independently the appropriate output voltage or de-emphasis setting, so the user is responsible for configuring these parameters. They can be set for each channel independently.

7.3.1.5 Reference Clock

A 25 MHz ±100-ppm reference clock is required for proper device operation. The DS110DF111 uses the reference clock to determine when its VCO is properly phase-locked to the incoming data-rate. The DS110DF111 does not include a crystal driver, so a stand-alone external oscillator is required.

The DS110DF111 is set to phase lock to a constrained set of data-rates, the digital circuitry in the device pre-configures the VCO frequency. This enables the DS110DF111 to detect very quickly that a loss of lock has occurred.

The phase noise of the reference clock is not critical. Any commercially-available 25 MHz oscillator (±100 ppm maximum) can provide an acceptable reference clock. The 25-MHz clock high level input voltage must match the VIN level used on the DS110DF111.

7.3.1.6 Control Pins

The 4-level input pins use a resistor divider to help set the 4 valid levels and provide a wider range of control settings when ENSMB=0. There is an internal 30K pull-up and a 60K pull-down connected to the package pin. These resistors, together with the external resistor connection combine to achieve the desired voltage level. Using the 1K pull-up, 1K pull-down, no connect, and 20K pull-down provide the optimal voltage levels for each of the four input states.

To minimize the startup current associated with the integrated 2.5-V regulator, the 1 K pull-up and pull-down resistors are recommended. If several 4-level inputs require the same setting, it is possible to combine two or more 1 K resistors into a single lower value resistor. As an example; combining two inputs with a single 500-Ω resistor is a good way to save board space.

7.3.1.7 Eye Opening Monitor

The DS110DF111’s Eye Opening Monitor (EOM) measures the internal data eye at the input of the CDR and can be used for 2 functions:

1. Horizontal Eye Opening (HEO) and Vertical Eye Opening (VEO) measurement
2. Full Eye Diagram Capture

The HEO measurement is made at the 0V crossing and is read in channel register 0x27. The VEO measurement is made at the 0.5 UI mark and is read in channel register 0x28. The HEO and VEO registers can be read from channel registers 0x27 and 0x28 at any time while the CDR is locked. The following equations are used to convert the contents of channel registers 0x27 and 0x28 into their appropriate units:

• HEO [UI] = ch reg 0x27 ÷ 64
• VEO [mV] = ch reg 0x28 x 3.125

A full eye diagram capture can be performed when the CDR is locked. The eye diagram is constructed within a 64 x 64 array, where each cell in the matrix consists of an 16-bit word. Users can manually adjust the vertical scaling of the EOM or allow the state machine to control the scaling which is the default option. The horizontal scaling controlled by the state machine and is always directly proportional to the data rate.

When a full eye diagram plot is captured, the retimer will shift out 4 16-bit words of junk data that should be discarded followed by 4096 16-bit words that make up the 64 x 64 eye plot. The first actual word of the eye plot from the retimer is for (X, Y) position (0,0). Each time the eye plot data is read out the voltage position is incremented. Once the voltage position has incremented to position 63, the next read will cause the voltage position to reset to 0 and the phase position to increment. This process will continue until the entire 64 x 64 matrix is read out. Figure 8 shows the EOM read out sequence overlaid on top of a simple eye opening plot. In this plot any hits are shown in green. This type of plot is helpful for quickly visualizing the HEO and VEO. Users can apply different algorithms to the output data to plot density or color gradients to the output data.

To manually control the EOM vertical range, remove scaling control from the state machine then select the desired range:

1. Channel Reg 0x2C[6] → 0
2. See Table 2

Table 2. Eye Opening Monitor Vertical Range Settings

CHANNEL REG 0x11[7:6] VALUE	EOM VERTICAL RANGE [mV]
2’b00	±100
2'b01	±200
2'b10	±300
2'b11	±400

The EOM operates as an under-sampled circuit. This allows the EOM to be useful in identifying over equalization, ringing and other gross signal conditioning issues. However, the EOM cannot be correlated to a bit error rate.

The EOM can be accessed in two ways to read out the entire eye plot:

• Multi-byte reads can be used such that data is repeatedly latched out from channel register 0x25.
• Or single byte reads. With single byte reads, the MSB are located in register 0x25 and the LSB are located in register 0x26. In this mode, the device must be addressed each time a new byte is read.

To perform a full eye capture with the EOM, follow these steps within the desired channel register set:

Table 5. 4-Level Inputs

LEVEL	SETTING	VOLTAGE
0	1K to GND	0.1 V
R	20K to GND	0.33 * VIN
Float	No connection	0.67 * VIN
1	1K to VIN	VIN - 0.05V

7.5.1.1 Address Lines

In either SMBus mode the DS110DF111 must be assigned a SMBus address. A unique address should be assigned to each device on the SMBus.

The SMBus address is latched into the DS110DF111 on power-up. The address is read in from the state of the ADR[1:0] lines upon power-up. A floating address line input will be interpreted as a logic 0.

The DS110DF111 can be configured with any of 4 SMBus addresses. The SMBus addressing scheme uses the least significant bit of the SMBus address as the Write/Read_N address bit. When an SMBus device is addressed for writing, this bit is set to 0; for reading, to 1. Table 6 shows the write address setting for the DS110DF111versus the values latched in on the address line at power-up.

7.5.1.2 Device Configuration in SMBus Slave Mode

The configurable settings of the DS110DF111 may be set independently for each channel at any time after power up using the SMBus. A register write is accomplished when the controller sends a START condition on the SMBus followed by the Write address of the DS110DF111 to be configured. See Table 6 for the mapping of the address lines to the SMBus Write addresses. After sending the Write address of the DS110DF111, the controller sends the register address byte followed by the register data byte. The DS110DF111 acknowledges each byte written to the controller according to the data link protocol of the SMBus Version 2.0 Specification. See this specification for additional information on the operation of the SMBus.

There are two types of device registers in the DS110DF111. These are the control/shared registers and the channel registers. The control/shared registers control or allow observation of settings which affect the operation of all channels of the DS110DF111. They are also used to select which channel of the device is to be the target channel for reads from and writes to the channel registers.

The channel registers are used to set all the configuration settings of the DS110DF111. They provide independent control for each channel of the DS110DF111 for all the settable device characteristics. Any registers not described in the tables that follow should be treated as reserved. The user should not try to write new values to these registers. The user-accessible registers described in the tables that follow provide a complete capability for customizing the operation of the DS110DF111 on a channel-by-channel basis.

7.5.1.3 Bit Fields in the Register Set

Many of the registers in the DS110DF111 are divided into bit fields. This allows a single register to serve multiple purposes, which may be unrelated. Often configuring the DS110DF111 requires writing a bit field that makes up only part of a register value while leaving the remainder of the register value unchanged.

7.5.1.4 Writing to and Reading From the Control/Shared Registers

Any write operation targeting register 0xff writes to the control/shared register 0xff. This is the only register in the DS110DF111 with an address of 0xff. Bit 2 of register 0xff is used to select either the control/shared register set or a channel register set. If bit 2 of register 0xff is cleared (written with a 0), then all subsequent read and write operations over the SMBus are directed to the control/shared register set. This situation persists until bit 2 of register 0xff is set (written with a 1). There is a register with address 0x00 in the control/shared register set, and there is also a register with address 0x00 in each channel register set. If you read the value in register 0x00 when bit 2 of register 0xff is cleared to 0, then the value returned by the DS110DF111 is the value in register 0x00 of the control/shared register set. If you read the value in register 0x00 when bit 2 of register 0xff is set to 1, then the value returned by the DS110DF111 is the value in register 0x00 of the selected channel register set. The channel register set is selected by bits 1:0 of register 0xff. If bit 3 of register 0xff is set to 1 and bit 2 of register 0xff is also set to 1, then any write operation to any register address will write all the channel register sets in the DS110DF111 simultaneously. This situation will persist until either bit 3 of register 0xff or bit 2 of register 0xff is cleared.

Note that when you write to register 0xff, independent of the current settings in register 0xff, the write operation ALWAYS targets the control/shared register 0xff. This channel select register, register 0xff, is unique in this regard. Table 7 shows the control/shared register set.

7.5.1.5 SMBus Strap Observation

Register 0x00, bits 7:4

In order to communicate with the DS110DF111 over the SMBus, it is necessary for the SMBus controller to know the address of the DS110DF111. The address strap observation bits in control/shared register 0x00 are primarily useful as a test of SMBus operation. In order to use the address strap observation bits of control/shared register 0x00, it is necessary first to set the diagnostic test control bits of control/shared register 0x06. This four bit field should be written with a value of 0xa. When this value is written to bits 3:0 of control/shared register 0x06, then the value of the SMBus address straps can be read in register 0x00, bits 7:4. The value read will be the same as the value present on the ADDR line when the DS110DF111 powers up. For example, if a value of 0x0 is read from control/shared register 0x00, bits 7:4, then at power-up the ADDR line was set to 0. The DS110DF111 is set to a SMBus Write address of 0x30.

7.5.1.6 Interrupt Channel Flag Bits

Register 0x05, bits 3:2

The operation of these bits is described in the section on interrupt handling later in this data sheet.

7.5.1.7 Control/Shared Register Reset

Register 0x04, bit 6

Register 0x04, bit 6, clears all the control/shared registers back to their factory defaults. This bit is self clearing, so it is cleared after it is written and the control/shared registers are reset to their factory default values.

7.5.1.8 Device Revision and Device ID

Register 0x01

Control/shared register 0x01 contains the device revision and device ID. The device ID will be different for the different devices in the retimer family. This register is useful because it can be interrogated by software to determine the device variant and revision installed in a particular system. The software might then configure the device with appropriate settings depending upon the device variant and revision.

7.5.1.9 Channel Select Register

Register 0xff, bits 3:0

Register 0xff, as described above, selects the channel or channels for channel register reads and writes. It is worth describing the operation of this register again for clarity. If bit 3 of register 0xff is set, then any channel register write applies to all channels. Channel register read operations always target only the channel specified in bits 1:0 of register 0xff regardless of the state of bit 3 of register 0xff. Read and write operations target the channel register sets only when bit 2 of register 0xff is set.

Bit 2 of register 0xff is the universal channel register enable. This bit must be set in order for any channel register reads and writes to occur. If this bit is set, then read operations from or write operations to register 0x00, for example, target channel register 0x00 for the selected channel rather than the control/shared register 0x00. In order to access the control/shared registers again, bit 2 of register 0xff should be cleared. Then the control/shared registers can again be accessed using the SMBus. Write operations to register 0xff always target the register with address 0xff in the control/shared register set. There is no other register, and specifically, no channel register, with address 0xff.

The contents of the channel select register, register 0xff, cannot be read back over the SMBus. Read operations on this register will always yield an invalid result. All eight bits of this register should always be set to the desired values whenever this register is written. Always write 0x0 to the four most significant bits of register 0xff. The register set target selected by each valid value written to the channel select register is shown in Table 8.

7.5.1.10 Resetting Individual Channels of the Retimer

Register 0x00, bit 2, and register 0x0a, bits 3:2

Bit 2 of channel register 0x00 is used to reset all the registers for the corresponding channel to their factory default settings. This bit is self-clearing. Writing this bit will clear any register changes you have made in the DS110DF111 since it was powered-up.

To reset just the CDR state machine without resetting the register values, which will re-initiate the lock and adaptation sequence for a particular channel, use channel register 0x0a. Set bit 3 of this register to enable the reset override, then set bit 2 to force the CDR state machine into reset. These bits can be set in the same operation. When bit 2 is subsequently cleared, the CDR state machine will resume normal operation. If a signal is present at the input to the selected channel, the DS110DF111 will attempt to lock to it and will adapt its CTLE and its DFE according to the currently configured adapt mode for the selected channel. The adapt mode is configured by channel register 0x31, bits 6:5.

7.5.1.11 Rate and Subrate Setting

Each channel of the DS110DF111 will, by default operate at 10.3125 Gbps and 1.25 Gbps. The device can be configured to operate at other VCO frequencies between 8.5 GHz and 11.3 GHz using the RATE (Reg: 0x2F bits [7:6]) and SUBRATE (Reg: 0x2F bits [5:4]) registers.

The DS110DF111 is designed to lock to signals conforming to several different data transmission standards. These standards may define a single data rate or multiple data rates. The rate and subrate settings of the DS110DF111 may be used to select a data transmission standard to which the input signal is expected to conform. The DS110DF111 searches each data rate applicable to the selected standard to find a valid signal to which it then phase locks.

The DS110DF111 is designed to lock to signals conforming to several different data transmission standards. These standards may define a single data rate or multiple data rates. The rate and subrate settings of the DS110DF111 are used to select which VCO divide ratios to enable. The DS110DF111 searches specific datarates within these enabled VCO divide ratios starting with divide by 8 and working up to divide by 1.

To select datarates based on frequencies other than the VCO defaults a group of PPM Counter registers (0x60 - 0x64) need to be reprogrammed.

To set the VCO Registers for other datarates within the VCO range, the formulas shown can be used to populate the Group 0/1 VCO programming registers.

7.5.1.12 Overriding the CTLE Boost Setting

Register 0x03, Register 0x2D, bit 3, and Register 0x3a

To override the adaptive CTLE boost settings, channel register 0x03 is used in conjuction with override register bit for the CTLE (0x2D[3]).

The current CTLE setting applied to the high-speed analog input can always be readback from register 0x52. This readback register value is valid for adaptive CTLE settings or when the override mechanism is enabled and the CTLE value from register 0x03 is being used.

When in divide by 4 or 8 VCO settings and data-rates the CTLE setting will not automatically adapt by default and channel register 0x3A comes into play. For short, low-loss input channels register 0x3A should be changed to a minimal CTLE value, writing register 0x3A = 00’h is recommended.

7.5.1.13 Overriding the Output Multiplexer

Register 0x09, bit 5, Register 0x14, bits 7:6, and Register 0x1e, bits 7:5

By default, the DS110DF111 output for each channel will be as shown in Table 15 and Table 16.

This default behavior can be modified by register writes. Register 0x1e, bits 7:5, contain the output multiplexer override value. The values of this three-bit field and the corresponding meanings of each are shown in Table 16.

When no signal is present at the input to the selected channel of the DS110DF111 the signal detect circuitry will power down the channel. This includes the output driver which is therefore muted when no signal is present at the input.

7.5.1.14 Overriding the VCO Divider Selection

Register 0x09, bit 2, and Register 0x18, bits 6:4

In normal operation, the DS110DF111 sets its VCO divider to the correct divide ratio, either 1, 2, 4, or 8 depending upon the bit rate of the signal at the channel input. It is possible to override the divider selection. This might be desired if the VCO is set to free run, for example, to output a signal at a subharmonic of the actual VCO frequency.

In order to override the VCO divider settings, first set bit 2 of register 0x09. This is the VCO divider override enable. Once this bit is set, the VCO divider setting is controlled by the value in register 0x18, bits 6:4. The valid values for this three-bit field are 0x0 to 0x3. The mapping of the bit field values to the divider ratio is shown in Table 17.

In normal operation, the DS110DF111 will determine the required VCO divider ratio automatically. In order for the DS110DF111 to acquire LOCK, the override divider selection must be included in the Group 0 VCO list for the current Rate/Subrate setting.

7.5.1.15 Using the Internal Eye Opening Monitor

Register 0x11, bits 7:6 and bit 5, Register 0x22, bit 7, Register 0x24, bit 7 and bit 0, Register 0x25, Register 0x26, Register 0x27, Register 0x28, Register 0x2a and Register 0x3e, bit 7

The DS110DF111 includes an internal eye opening monitor. The eye opening monitor is used by the retime to compute a figure of merit for automatic adaptation of the CTLE and the DFE. It can also be controlled and queried through the SMBus by a system controller.

The eye opening monitor produces error hit counts for settable phase and voltage offsets of the comparator in the retimer. This is similar to the way many Bit Error Rate Test Sets measure eye opening. At each phase and amplitude offset setting, the eye opening monitor determines the nominal bit value (“0” or “1”) using its primary comparator. This is the bit value that is resynchronized to the recovered clock and presented at the output of the DS110DF111. The eye opening monitor also determines the bit value detected by the offset comparator. This information yields an eye contour. Here's how this works.

If the offset comparator is offset in voltage by an amount larger than the vertical eye opening, for example, then the offset comparator will always decide that the current bit has a bit value of “0”. When the bit is really a “1”, as determined by the primary comparator, this is considered a bit error. The number of bit errors is counted for a settable interval at each setting of the offset phase and voltage of the offset comparator. These error counts can be read from registers 0x25 and 0x26 for sequential phase and voltage offsets. These error counts for all phase and voltage offsets form a 64 X 64 point array. A surface or contour plot of the error hit count versus phase and voltage offset produces an eye diagram, which can be plotted by external software.

The eye opening monitor works in two modes. In the first, only the horizontal and vertical eye openings are measured. The eye opening monitor first sweeps its variable-phase clock through one unit interval with the comparison voltage set to the mid-point of the signal. This determines the mid-point of the horizontal eye opening. The eye opening monitor then sets its variable phase clock to the mid-point of the horizontal eye opening and sweeps its comparison voltage. These two measurements determine the horizontal and vertical eye openings. The horizontal eye opening value is read from register 0x27 and the vertical eye opening from register 0x28. Both values are single byte values.

The measurement of horizontal and vertical eye opening is very fast. The speed of this measurement makes it useful for determining the adaptation figure of merit. In normal operation, the HEO and VEO are automatically measured periodically to determine whether the DS110DF111 is still in lock. Reading registers 0x27 and 0x28 will yield the most-recently measured HEO and VEO values.

In normal operation, the eye monitor circuitry is powered down most of the time to save power. When the eye is to be measured under external control, it must first be enabled by writing a 0 to bit 5 of register 0x11. The default value of this bit is 1, which powers down the eye monitor except when it is powered-up periodically by the CDR state machine and used to test CDR lock. The eye monitor must be powered up to measure the eye under external SMBus control.

Bits 7:6 of register 0x11 are also used during eye monitor operation to set the EOM voltage range. This is described below. A single write to register 0x11 can set both bit 5 and bits 7:6 in one operation.

Register 0x3e, bit 7, enables horizontal and vertical eye opening measurements as part of the lock validation sequence. When this bit is set, the CDR state machine periodically uses the eye monitor circuitry to measure the horizontal and vertical eye opening. If the eye openings are too small, according to the pre-determined thresholds in register 0x6a, then the CDR state machine declares lock loss and begins the lock acquisition process again. For SMBus acquisition of the internal eye, this lock monitoring function must be disabled. Prior to overriding the EOM by writing a 1 to bit 0 of register 0x24, disable the lock monitoring function by writing a 0 to bit 7 of register 0x3e.

Once the eye has been acquired, you can reinstate HEO and VEO lock monitoring by once again writing a 1 to bit 7 of register 0x3e. Under external SMBus control, the eye opening monitor can be programmed to sweep through all its 64 states of phase and voltage offset autonomously. This mode is initiated by setting register 0x24, bit 7, the fast_eom mode bit.

Register 0x11, bits 7:6 and bit 5, Register 0x22, bit 7, Register 0x24, bit 7 and bit 0, Register 0x25, Register 0x26, Register 0x27, Register 0x28, Register 0x2a and Register 0x3e, bit 7

Register 0x22, bit 7, the eom_ov bit, should be cleared in this mode. When the fast_eom bit is set, the eye opening monitor operation is initiated by setting bit 0 of register 0x24, which is self-clearing. As soon as this bit is set, the eye opening monitor begins to acquire eye data. The results of the eye opening monitor error counter are stored in register 0x25 and 0x26. In this mode the eye opening monitor results can be obtained by repeated multi-byte reads from register 0x25. It is not necessary to read from register 0x26 for a multi-byte read. As soon as the eight most significant bits are read from register 0x25, the eight least significant bits for the current setting are loaded into register 0x25 and they can be read immediately. As soon as the read of the eight most significant bits has been initiated, the DS110DF111 sets its phase and voltage offsets to the next setting and starts its error counter again. The result of this is that the data from the eye opening monitor is available as quickly as it can be read over the SMBus with no further register writes required. The external controller just reads the data from the DS110DF111 over the SMBus as fast as it can. When all the data has been read, the DS110DF111 clears the eom_start bit.

If multi-byte reads are not used, meaning that the device is addressed each time a byte is read from it, then it is necessary to read register 0x25 to get the MSB (the eight most significant bits) and register 0x26 to get the LSB (the eight least significant bits) of the current eye monitor measurement. Again, as soon as the read of the MSB has been initiated, the DS110DF111 sets its phase and voltage offsets to the next setting and starts its error counter again. In this mode both registers 0x25 and 0x26 must be read in order to get the eye monitor data. The eye monitor data for the next set of phase and voltage offsets will not be loaded into registers 0x25 and 0x26 until both registers have been read for the current set of phase and voltage offsets. In all eye opening monitor modes, the amount of time during which the eye opening monitor accumulates eye opening data can be set by the value of register 0x2a. In general, the greater this value the longer the accumulation time. When this value is set to its maximum possible value of 0xff, the maximum number of samples acquired at each phase and amplitude offset is approximately 218. Even with this setting, the eye opening monitor values can be read from the SMBus with no delay. The eye opening monitor operation is sufficiently fast that the SMBus read operation cannot outrun it.

The eye opening is measured at the input to the data comparator. At this point in the data path, a significant amount of gain has been applied to the signal by the CTLE. In many cases, the vertical eye opening as measured by the EOM will be on the order of 400 to 500 mV peak-to-peak. The secondary comparator, which is used to measure the eye opening, has an adjustable voltage range from ±100 mV to ±400 mV. The EOM voltage range is normally set by the CDR state machine during lock and adaptation, but the range can be overridden by writing a two-bit code to bits 7:6 of register 0x11. The values of this code and the corresponding EOM voltage ranges are shown in Table 18.

Note that the voltage ranges shown in Table 18 are the voltage ranges of the signal at the input to the data path comparator. These values are not directly equivalent to any observable voltage measurements at the input to the DS110DF111. Note also that if the EOM voltage range is set too small the voltage sweep of the secondary comparator may not be sufficient to capture the vertical eye opening. When this happens the eye boundaries will be outside the vertical voltage range of the eye measurement.

To summarize, the procedure for reading the eye monitor data from the DS110DF111is shown below.

1. Select the DS110DF111 channel to be used for the eye monitor measurement by writing the channel select register, register 0xff, with the appropriate value as shown in Table 8 if the correct channel register set is already selected, this step may be skipped.
2. Select the eye monitor voltage range by setting bits 7:6 of register 0x11 according to the values in Table 18. The CDR state machine will have set this range during lock acquisition, but it may be necessary to change it to capture the entire vertical eye extent.
3. Power up the eye monitor circuitry by clearing bit 5 of register 0x11. Normally the eye monitor circuitry is powered up periodically by the CDR state machine. Clearing bit 5 of register 0x11 enables the eye monitor circuitry unconditionally. This bit should be set again once the eye acquisition is complete. Clearing bit 5 and setting bits 7:6 of register 0x11 as desired can be combined into a single register write if desired.
4. Clear bit 7 of register 0x22. This is the eye monitor override bit. It is cleared by default, so you may not need to change it.
5. Set bit 7 of register 0x24. This is the fast eye monitor enable bit.
6. Set bit 1 of register 0x24. This initiates the automatic fast eye monitor measurement. This bit can be set at the same time a bit 7 of register 0x24 if desired.
7. Read the data array from the DS110DF111. This can be accomplished in two ways.
   • If you are using multi-byte reads, address the DS110DF111 to read from register 0x25. Continue to read from this register without addressing the device again until you have read all the data desired. The read operation can be interrupted by addressing the device again and then resumed by reading once again from register 0x25.
   • If you are not using multi-byte reads, then read the MSB for each phase and amplitude offset setting from register 0x25 and the LSB for each setting from register 0x26. In this mode, you address the device each time you want to read a new byte.
8. In either mode, the first four bytes do not contain valid data. These should be discarded.
9. Continue reading eye monitor data until you have read the entire 64X64 array.
10. Clear bit 7 of register 0x24. This disables fast eye monitor mode.
11. Set bit 5 of register 0x11. This will return control of the eye monitor circuitry to the CDR state machine.
12. Set bit 7 of register 0x3e. This re-enables the HEO and VEO lock monitoring.

7.5.1.16 Overriding the DFE Tap Weights and Polarities

Register 0x11, bits 3:0, Register 0x12, bit 7 and bits 4:0, Register 0x15, bit 7, Register 0x1e, bit 3, Register 0x20, Register 0x21, Register 0x23, bit 6, Register 0x24, bit 2, Register 0x2f, bit 0, and Registers 0x71–0x75

For the DS110DF111 the DFE tap weights and polarities are normally set automatically by the adaptation procedure. These values can be overridden by the user if desired.

Prior to overriding the DFE tap weights and polarities, the dfe_ov bit, bit 6 of register 0x23, should be set. This bit is set by default. In order for the DFE tap weights and polarities to be applied to the input signal, bit 3 of register 0x1e, the dfe_PD bit, which powers down the DFE, should be cleared. This bit is cleared by default. It is not necessary to change the default settings of these registers, but verify that they are set as described.

It is necessary to set bit 7 of register 0x15 to manually set the DFE tap weights. This bit is cleared by default.

Bits 4:0 of register 0x12 set the five-bit weight for DFE tap 1. The first DFE tap has a five-bit setting, while the other taps are set using four bits. Often the first DFE tap has the largest effect in improving the bit error rate of the system, which is why this tap has a five-bit weight setting.

The polarity of the tap weight for tap 1 is set using bit 7 of the same register, register 0x12. The polarity is set to 0 by default, which corresponds to a negative algebraic sign for the tap.

The other four taps are set using four-bit fields in registers 0x20 and 0x21. The polarities of these taps are set by bits 3:0 in register 0x11. These tap polarities are all set to 0 by default.

As is the case for the CTLE settings, if changing the DFE tap weights or polarities causes the DS110DF111 to lose lock, it may readapt its CTLE in order to reacquire lock. If this occurs, the CTLE settings may appear to change spontaneously when the DFE tap weights are changed. The mechanism is the same as that described above for the CTLE boost settings.

When the DS110DF111 is set to adapt mode 2 or 3 using bits 6:5 of register 0x31, it will automatically adapt its DFE whenever its CDR state machine is reset. This occurs when the user manually resets the CDR state machine using bits 3:2 of register 0x0a, or when a signal is first presented at the input to the channel when the channel is in an unlocked state.

Regardless of the adapt mode, DFE adaptation can be initiated under SMBus control. Because the DFE tap weight registers are used by the DFE state machine during adaptation, they may be reset prior to adaptation, which can cause the adaptation to fail. The DFE tap observation registers can be used to prevent this.

Prior to initiating DFE adaptation under SMBus control, write the starting values of the DFE tap settings into the DFE tap weight registers, registers 0x11, 0x12, 0x20, and 0x21. The values can be read from the observation registers, registers 0x71 through 0x75. For each DFE tap, read the current value in the observation register. Both the polarities and the tap weights are contained in the observation registers. For each DFE tap, write the current tap polarity and tap weight into the DFE tap register. Once all these values have been written, DFE adaptation can be initiated and it will proceed normally. If the DS110DF111 fails to find a set of DFE tap weights producing a better adaptation figure of merit than the starting tap weights, the starting tap weights will be retained and used.

CTLE adaptation can also be initiated manually. Setting and then clearing bit 0 of register 0x2f will initiate adaptation of the CTLE. As with the DFE, if the DS110DF111 fails to find a set of CTLE settings that produce a better adaptation figure of merit than the starting CTLE values, the starting CTLE values will be retained and used.

7.5.1.17 Enabling Slow Rise/Fall Time on the Output Driver

Register 0x18, bit 2

Normally the rise and fall times of the output driver of the DS110DF111 are set by the slew rate of the output transistors. By default, the output transistors are biased to provide the maximum possible slew rate, and hence the minimum possible rise and fall times. In some applications, slower rise and fall times may be desired. For example, slower rise and fall times may reduce the amplitude of electromagnetic interference (EMI) produced by a system.

Setting bit 2 of register 0x18 will adjust the output driver circuitry to increase the rise and fall times of the signal. Setting this bit will approximately double the nominal rise and fall times of the DS110DF111 output driver. This bit is cleared by default.

7.5.1.18 Using the PRBS Generator

Register 0x1e, bits 7 and 4, Register 0x30, and Register 0x0d

Notes:

1. To select PRBS31 instead of PRBS9, change Register Data 0x30 = 0x02 with mask of 0x03 in Step 6.
2. To only select Channel A, change Register Data 0xFF = 0x04 in Step 1.
3. To only select Channel B, change Register Data 0xFF = 0x05 in Step 1.
4. It has been noted in product testing that some pattern analyzers use an alternate PRBS9 polarity.

Notes:

1. To select PRBS31 instead of PRBS9, change Register Data 0x30 = 0x0A in Step 13.
2. To achieve a higher data-rate in Step 6 decrease VCO cap count value.
3. To achieve a lower data-rate in Step 6 increase the VCO cap count value.
4. To only select Channel A, change Register Data 0xFF = 0x04 in Step 1.
5. To only select Channel B, change Register Data 0xFF = 0x05 in Step 1.
6. With a free running VCO the actual output frequency will change with temperature and voltage. BERT is not recommended in this mode.

7.5.1.19 Inverting the Output Polarity

Register 0x1f, bit 7

In some systems, the polarity of the data does not matter. In systems where it does matter, it is sometimes necessary, for the purposes of trace routing, for example, to invert the normal polarities of the data signals.

The DS110DF111 can invert the polarity of the data signals by means of a register write. Writing a 1 to bit 7 of register 0x1f inverts the polarity of the output signal for the selected channel. This can provide additional flexibility in system design and board layout.

7.5.1.20 Overriding the Figure of Merit Adaption

Register 0x2c, bits 5:4, Register 0x31, bits 6:5, Register 0x6b, Register 0x6c, Register 0x6d, and Register 0x6e, bits 7 and 6

The default figure of merit for both the CTLE and DFE adaptation is simple. The horizontal and vertical eye openings are measured for each CTLE boost setting or set of DFE tap weights and polarities. The vertical eye opening is scaled to a constant reference vertical eye opening and the smaller of the horizontal or vertical eye opening is taken as the figure of merit for that set of equalizer settings. The objective is to adapt the equalizer to a point where the horizontal and vertical eye openings are both large and approximately equal in magnitude. This usually provides optimum bit error rate performance for most transmission channels.

In the DS110DF111 the CTLE figure of merit type is selected using the two-bit field in register 0x31, bits 6:5. The CTLE will not adapt by default when VCO/4 or VCO/8 data-rate is used. In this case the CTLE value will be taken directly from register 0x3A.

For some transmission media the adaptation can reach a better setting if a different figure of merit is used. The DS110DF111 includes the capability of adapting based on a configurable figure of merit. The configurable figure of merit is structured as shown in Equation 1:

In order to use the configurable figure of merit, the enable bits must be set. To use the configurable figure of merit for the CTLE adaptation, set bit 7 of register 0x6e. To use the configurable figure of merit for the DFE adaptation, set bit 6 of register 0x6e. The same scaling factors are used for both CTLE and DFE adaptation when the configurable figure of merit is enabled.

7.5.1.21 Setting the Rate and Subrate for Lock Acquisition

Register 0x2f, bits 7:6

The rate and subrate settings, which constrain the data rate search can be set using channel register 0x2f. Bits 7:6 are RATE<1:0>, and bits 5:4 are SUBRATE<1:0>.

7.5.1.22 Setting the Adaption/Lock Mode

Register 0x31, bits 6:5, and Register 0x33, bits 7:4 and 3:0, Register 0x34, bits 3:0, Register 0x35, bits 4:0, Register 0x3e, bit 7, and Register 0x6a

There are four adaptation modes available in the DS110DF111.

• Mode 0: The user is responsible for setting the CTLE and DFE (for the DS110DF111) values. This mode is used if the transmission channel response is fixed.
• Mode 1: Only the CTLE is adapted to equalize the transmission channel. The DFE is enabled , but the tap weights are all set to 0. This mode is primarily used for smoothly-varying high-loss transmission channels such as cables and simple PCB traces.
• Mode 2: In this mode, both the CTLE and the DFE are adapted to compensate for additional loss, reflections, and crosstalk in the input transmission channel. The maximum DFE tap weights can be constrained using register 0x34, bits 3:0, and register 0x35, bits 4:0.
• Mode 3: In this mode, both the CTLE and DFE are adapted as in mode 2. However, in mode 3, more emphasis is placed on the DFE setting. This mode may give better results for high crosstalk transmission channels.

Bits 6:5 of register 0x31 determine the adaptation mode to be used. The mapping of these register bits to the adaptation algorithm is shown in.

By default the DS110DF111 requires that the equalized internal eye exhibit horizontal and vertical eye openings greater than a pre-set minimum in order to declare a successful lock. The minimum values are set in register 0x6a.

The DS110DF111 continuously monitors the horizontal and vertical eye openings while it is in lock. If the eye opening falls below the threshold set in register 0x6a, the DS110DF111 will declare a loss of lock.

The continuous monitoring of the horizontal and vertical eye openings may be disabled by clearing bit 7 of register 0x3e.

7.5.1.23 Initiating Adaption

Register 0x24, bit 2, and Register 0x2f, bit 0

When the DS110DF111 becomes unlocked, it will automatically try to acquire lock. If an adaptation mode is selected using bits 6:5 in register 0x31, the DS110DF111 will also try to adapt its CTLE and DFE.

Adaptation can also be initiated by the user. CTLE adaptation can be initiated by setting and then clearing register 0x2f, bit 0. In the DS110DF111, DFE adaptation can be initiated by setting and then clearing bit 2 of register 0x24.

7.5.1.24 Overriding the CTLE Settings used for CTLE Adaption

Register 0x2c, bits 3:0, Register 0x2f, bit 3, Register 0x39, bits 4:0, and Registers 0x40-0x4f

The CTLE adaptation algorithm operates by setting the CTLE boost stage controls to a set of pre-determined boost settings, each of which provides progressively more high-frequency boost. At each stage in the adaptation process, the DS110DF111 attempts to phase lock to the equalized signal. If the phase lock succeeds, the DS110DF111 measures the horizontal and vertical eye openings using the internal eye monitor circuit. The DS110DF111 computes a figure of merit for the eye opening and compares it to the previous best value of the figure of merit. While the figure of merit continues to improve, the DS110DF111 continues to try additional values of the CTLE boost setting until the figure of merit ceases to improve and begins to degrade. When the figure of merit starts to degrade, the DS110DF111 still continues to try additional CTLE settings for a pre-determined trial count called the “look-beyond” count, and if no improvement in the figure of merit results, it resets the CTLE boost values to those that produced the best figure of merit. The resulting CTLE boost values are then stored in register 0x03. The “look-beyond” count is configured by the value in register 0x2c, bits 3:0. The value is 0x2 by default.

The set of boost values used as candidate values during CTLE adaptation are stored as bit fields in registers 0x40-0x4F. The default values for these settings are shown in Table 23. These values may be overridden by setting the corresponding register values over the SMBus. If these values are overridden, then the next time the CTLE adaptation is performed the set of CTLE boost values stored in these registers will be used for the adaptation. Resetting the channel registers by setting bit 2 of channel register 0x00 will reset the CTLE boost settings to their defaults. So will power-cycling the DS110DF111.

As an alternative to, or in conjunction with, writing the CTLE boost setting registers 0x40 through 0x4F, it is possible to set the starting CTLE boost setting index. To override the default setting, which is 0, set bit 3 of register 0x2F. When this bit is set, the starting index for adaptation comes from register 0x39, bits 4:0. This is the index into the CTLE settings table in registers 0x40 through 0x4F. When this starting index is 0, which is the default, CTLE adaptation starts at the first setting in the table, the one in register 0x40, and continues until the optimum FOM is reached.

7.5.1.25 Setting the Output Differential Voltage

Register 0x2d, bits 2:0

There are eight levels of output differential voltage available in the DS110DF111, from 0.6 V to 1.3 V in 0.1 V increments. The values in bits 2:0 of register 0x2d set the output VOD. The available VOD settings and the corresponding values of this bit field are shown in Table 24. Not all VOD levels are available using the VODA/B control terminals.

7.5.1.26 Setting the Output De-Emphasis Setting

Register 0x15, bits 2:0 and bit 6

Fifteen output de-emphasis settings are available in the DS110DF111, ranging from 0 dB to -12 dB. The de-emphasis values come from register 0x15, bits 2:0 and register 0x15, bit 6, which is the de-emphasis range bit. The available driver de-emphasis settings and the mapping to these bits are shown in Table 25.

7.5.1.27 CTLE Setting for Divide by 4 and Divide by 8 VCO Ranges

Register 0x3a, bits 7:0

In the DS110DF111 the default CTLE setting for lower speed signals is taken directly from register 0x3a and is not automatically adapted. For short, low loss input channels this value may need to be decreased from the default (A5'h) CTLE setting.

Table 26. Channel Register Definition

ADDRESS (HEX)	DEFAULT VALUE (HEX)	BITS	DEFAULT VALUE (BINARY)	EEPROM	MODE	DESCRIPTION
0x00	00	2	0	N	R/W/SC	Reset Channel Registers to Defaults (Self-clearing)
0x01	00	4	0	N	R	CDR Lock Loss Interrupt
		0	0			Signal Detect Loss Interrupt
0x02	00	7:0	00’h	N	R	CDR Status [7:0] Bit[7] = Reserved Bit[6] = Reserved Bit[5] = Fail Lock Check Bit[4] = Lock Bit[3] = CDR Lock Bit[2] = Reserved Bit[1] = Reserved Bit[0] = Reserved
0x03	00	7:6	00	Y	R/W	Used for setting CTLE value when Channel Register 0x2D[3] is high. Read-back value going to analog in Channel Register 0x52. CTLE Boost Stage [0] <1:0> Bits [7:6] CTLE Boost Stage [1] <1:0> Bits [5:4] CTLE Boost Stage [2] <1:0> Bits [3:2] CTLE Boost Stage [3] <1:0> Bits [1:0]
		5:4	00	Y	R/W
		3:2	00	Y	R/W
		1:0	00	Y	R/W
0x08	00	7:5	000	N	R/W	Reserved
		4:0	00000	Y	R/W	CDR Cap_DAC Start Group 0
0x09	00	7	0	Y	R/W	Reserved
		6	0	Y	R/W	Reserved
		5	0	Y	R/W	Enable Override Output Mux (Register 0x1E[7:5])
		4:3	00	Y		Reserved
		2	0	Y		Enable Override Divider Select (Register 0x18[6:4])
		1:0	00	Y		Reserved
0x0A	10	7:5	000	Y	R/W	Reserved
		4	1	Y		Reserved
		3	0	Y		Enable CDR Reset Override (Register 0x0A[2])
		2	0	Y		CDR Reset Override Bit
		1:0	00	Y		Reserved
0x0B	0F	7:5	000	N	R/W	Reserved
		4:0	1111	Y	R/W	CDR Cap_DAC Start Group 1
0x0C	08	7:4	0000		R/W	Status Control[3:0]
		3	1	N	R/W	Single Bit Transition Detector – Lock Qualification 1: Enables SBT 0: Disables SBT
		2	0	Y		Reserved
		1:0	00	N		Reserved
0x0D	00	7:6	00	N	R/W	Reserved
		5	0	Y		PRBS pattern shift Enable. Use in conjunction with 0x1E[4] and 0x30[3] to start PRBS. Note: This bit must be set high last.
		4:0	00000	N		Reserved
0x0E	93	7:0	1001 0011	Y	R/W	Reserved
0x0F	69	7:0	0110 1001	Y	R/W	Reserved
0x10	3A	7:5	001	Y	R/W	Reserved
		4:0	11010
0x11	20	7:6	00	Y	R/W	Eye Opening Monitor Voltage Range <1:0> 00: 3.125 mV 01: 6.250 mV 10: 9.375 mV 11: 12.500 mV
		5	1	Y		Eye Opening Monitor Power Down
		4	0	N	R/W	Reserved
		3	0	Y	R/W	DFE Tap 2 Polarity (Use w/manual DFE override, 0x15[7])
		2	0	Y		DFE Tap 3 Polarity (Use w/manual DFE override, 0x15[7])
		1	0	Y		DFE Tap 4 Polarity (Use w/manual DFE override, 0x15[7])
		0	0	Y		DFE Tap 5 Polarity (Use w/manual DFE override, 0x15[7])
0x12	A0	7	1	Y	R/W	DFE Tap 1 Polarity (Use w/manual DFE override, 0x15[7])
		6	0	N	R/W	Reserved
		5	1	Y	R/W	DFE Select negative gm
		4:0	00000	Y		DFE Tap 1 Weight <4:0>
0x13	90	7	1	N	R/W	Reserved
		6	0	Y
		5	0	N	R/W
		4	1	Y	R/W	Enable DC offset control
		3	0	Y	R/W	Reserved
		2	0	Y	R/W	CTLE Boost Stage 3, Bit 2 (Limiting Bit)
		1	0	Y	R/W	Enable DWDM Mode
		0	0	Y	R/W	Reserved
0x14	00	7	0	Y	R/W	Force Signal Detect On
		6	0	Y	R/W	Force Signal Detect Off
		5:4	00	Y	R/W	Signal Detect – Assert Reference Levels
		3:2	00	Y	R/W	Signal Detect – De-assert Reference Levels
		1:0	00	N		Reserved
0x15	10	7	0	Y	R/W	Enables manual DFE tap settings Use with 0x11[3:0], 0x12[7], 0x12[4:0], 0x20[7:0], 0x21[7:0]
		6	0	Y	R/W	Compress the range of de-emphasis to 0-6 dB
		5	0			Reserved
		4	1			Reserved
		3	0	Y	R/W	Driver Power-Down
		2:0	000	Y	R/W	Driver De-emphasis Setting<2:0>; 0dB - 12dB; See Table 25
0x16	7A	7:4	0111	Y	R/W	Reserved
		3:0	1010	Y
0x17	25	7:4	0010	Y	R/W	Reserved
		3:0	0101	Y
0x18	40	7	0	N	R/W
		6:4	100	Y		VCO Divider Ratio <2:0> (Enable from Register 0x09, Bit 2) 000: Full-Rate 001: Divide by 2 010: Divide by 4 011: Divide by 8 100: Default value at power up
		3	0	N
		2	0	N	R/W	Enable slow rise/fall time edge rate
		1:0	00	N	R/W	Reserved
0x19	23	7:6	00	N	R/W	Reserved
		5:0	100011	Y
0x1A	00	7:4	0000	Y	R/W	Reserved
		3:0	0000	N
0x1B	03	7:2	000000	N	R/W	Reserved
		1:0	11	Y
0x1C	24	7:5	001	Y	R/W	Reserved
		4:2	001
		1:0	00
0x1D	00	7	0	Y	R/W	Reserved
		6:0	000000	N
0x1E	E1	7:5	111	Y	R/W	Selects active PFD MUX input 000: Raw Data 001: Re-timed Data 100: PRBS Generator 111: Mute
		4	0	N	R/W	Enable the PRBS serializer, used with 0x1E[7:5], 0x30[3:0], 0x0D[5]
		3	0	Y	R/W	Disable the DFE function (Disable = 1)
		2:1	00			Reserved
		0	1			Reserved
0x1F	55	7	0	Y	R/W	Invert the polarity of the driver
		6	1			Reserved
		5:0	010101	N		Reserved
0x20	00	7:4	0000	Y	R/W	DFE Tap 5 Weight <3:0> (Use w/manual DFE override, 0x15[7])
		3:0	0000	Y		DFE Tap 4 Weight <3:0> (Use w/manual DFE override, 0x15[7])
0x21	00	7:4	0000	Y	R/W	DFE Tap 3 Weight <3:0> (Use w/manual DFE override, 0x15[7])
		3:0	0000	Y		DFE Tap 2 Weight <3:0> (Use w/manual DFE override, 0x15[7])
0x22	00	7	0	Y	R/W	Eye Monitor override
		6	0	Y		Reserved
		5:0	00000	N		Reserved
0x23	40	7	0	Y	R/W	Eye Monitor Get HEO VEO override
		6	1	Y	R/W	DFE Override
		5:0	000000	N	R/W	Eye Monitor VDAC
0x24	00	7	0	N	R/W	Enable Fast Eye Opening Monitor Mode
		6	0	N	R	DFE Error - No Lock
		5	0	N	R	Get HEO VEO Error - No hits at crossing
		4	0	N	R	Get HEO VEO Error - Vertical Eye not visible
		3	0	N	R/W	Reserved
		2	0	N	R/W/SC	Start DFE Adaptation (Self- Clearing)
		1	0	N	R/W/SC	Start Get HEO VEO Measurement (Self- Clearing)
		0	0	N	R/W/SC	Start Eye Opening Monitor Counter (Self-Clearing)
0x25	00	7:0	00’h	N	R	Eye Opening Monitor Count <15:8>
0x26	00	7:0	00’h	N	R	Eye Opening Monitor Count <7:0>
0x27	00	7:0	00’h	N	R	HEO Value <7:0> (Measured in 0-63 phase settings)
0x28	00	7:0	00’h	N	R	VEO Value <7:0>
0x29	00	7	0	N	R/W	Reserved
		6:5	00		R	Eye Opening Monitor Voltage Range Setting <1:0> See 0x11[7:6]
		4:0	00000		R/W	Reserved
0x2A	30	7:0	30’h	Y	R/W	Eye Opening Monitor Timer Threshold <7:0>
0x2B	00	7:6	00	N	R/W	Reserved
		5:4	00	Y		Reserved
		3:0	0000	Y		Minimum hits for HEO-VEO hit counter
0x2C	72	7	0	N	R/W	Reserved
		6	1	Y		Scale VEO based on Eye Monitor Vrange
		5:4	11	Y		DFE Adaptation Figure of Merit Type <1:0> 00: Not Valid 01: State Machine uses only HEO 10: State Machine uses only VEO 11: State Machine uses both HEO and VEO
		3:0	0010	Y		Determines number of DFE settings to look-beyond current best Figure of Merit (FOM)
0x2D	80	7	1	Y	R/W	Enable Driver Short Circuit protection
		6	0			Enable FAST signal detect
		5	0			Increase the Assert and De-assert reference thresholds
		4	0			Set high (1) to decrease the signal detect gain
		3	0			Set high (1) to override the EQ setting going to the analog from 0x03[7:0]
		2:0	000			Output Driver VOD [2:0] 000: 600 mV 001: 700 mV 010: 800 mV 011: 900 mV 100: 1000 mV 101: 1100 mV 110: 1200 mV 111: 1300 mV
0x2E	00	7:6	00	N	R/W	Reserved
		5	0	Y
		4:3	00	N
		2	0	Y
		1:0	00	N
0x2F	06	7:6	00	Y	R/W	RATE <1:0>
		5:4	00			SUBRATE <1:0>
		3	0			CTLE Adaptation Index Override 0: CTLE adaption will start at Reg_0x40 + Reg_0x39[3:0]. So this may be used to preclude lower CTLE settings. 1: CTLE will not adapt and will use the CTLE setting of Reg_0x40 + Reg_0x39[3:0] for scalar divide ratios of 1 or 2. Divide ratios of 4 & 8 will take CTLE settings from 0x3A unless 0x55[0] is high, which will revert to the setting in Reg_0x40 + Reg_0x39[3:0].
		2	1			Enable PPM Check - for Lock qualifier
		1	1			Enable FLD Check - for Lock qualifier
		0	0	N	R	Start CTLE Adaptation
0x30	00	7:6	00	N	R/W	Reserved
		5	0		R	Reserved
		4	0		R	Goes High if Interrupt from CDR Goes High
		3	0	Y	R/W	Enable PRBS digital CLK
		2	0	N		Reserved
		1:0	00	Y		PRBS Pattern[1:0]
0x31	40	7	0	Y	R/W	Reserved
		6:5	10			Adaptation Mode <1:0> 00: No adaption 01: Adapt only CTLE till optimal 10: Adapt CTLE till optimal, then DFE, then CTLE again 11: Adapt CTLE till LOCK, then DFE, then CTLE till optimal
		4:3	00	Y	R/W	CTLE Adaptation Figure of Merit Type <1:0> 00: SM uses both HEO and VEO 01: SM uses only HEO 10: SM uses only VEO 11: SM uses both HEO and VEO
		2:0	000	N		Reserved
0x32	11	7:4	0001	Y	R/W	HEO Interrupt Threshold <3:0> Compares HEO value, Reg_0x27[7:0] vs. threshold of Reg_0x32[7:4]*4
		3:0	0001	Y	R/W	VEO Interrupt Threshold <3:0> Compares VEO value, Reg_0x28[7:0] vs. threshold of Reg_0x32[3:0]*4
0x33	88	7:4	1000	Y	R/W	HEO Threshold for CTLE Adaptation Handoff to DFE Adaptation Compares HEO value, Reg_0x27[7:0] vs. threshold of Reg_0x33[7:4]*2
		3:0	1000	Y	R/W	VEO Threshold for CTLE Adaptation Handoff to DFE Adaptation Compares HEO value, Reg_0x27[7:0] vs. threshold of Reg_0x33[3:0]*2
0x34	3F	7	0	N	R	PPM Error Ready
		6	0	Y	R/W	Low power disable
		4:5	11			Lock Counter
		3:0	1111			Maximum DFE Tap Absolute Value for Taps 2–5 <3:0>
0x35	1F	7:6	00	Y	R/W
		5	0			Get PPM Error from PPM count - clears when done
		4:0	1 1111			Maximum DFE Tap Absolute Value for Tap 1 <4:0>
0x36	33	7	0	Y	R/W	Reserved
		6	0			Enable HEO/VEO Interrupt
		5:4	11	Y		Reserved
		3	0	N		Reserved
		2	0	Y		Cap DAC range override enable
		1:0	11	Y		Cap DAC range[1:0]
0x37	00	7:0	00'h	N	R	CTLE Status
0x38	00	7:0	00'h	N	R	DFE Status
0x39	00	7	0	N	R/W	Reserved
		6:5	00	Y		Reserved
		4:0	0 0000			Start Index for CTLE Adaptation <4:0> (Enable from Register 0x2f, Bit 3)
0x3A	A5	7:6	10	Y	R/W	Fixed CTLE Stage 0 Boost Setting for Divide Ratios 4 and 8 <1:0>
		5:4	10		R/W	Fixed CTLE Stage 1 Boost Setting for Divide Ratios 4 and 8 <1:0>
		3:2	01		R/W	Fixed CTLE Stage 2 Boost Setting for Divide Ratios 4 and 8 <1:0>
		1:0	01		R/W	Fixed CTLE Stage 3 Boost Setting for Divide Ratios 4 and 8 <1:0> Note: For VCO/4 and VCO/8 tuning ranges the CTLE will not adapt, instead the CTLE setting is taken directly from this register. Shorter, low-loss channels should write a value of 00'h into this register.
0x3B	00	7:0	00'h	N	R	PPM Count MSB
0x3C	00	7:0	00'h	N	R	PPM Count LSB
0x3D	00	7	0	Y	R/W	Reserved
		6:0	000000	N
0x3E	80	7	1	Y	R/W	Enable HEO/VEO lock monitoring once SBT/FLD declare lock. Once the lock and adaptation processes are complete, HEO/VEO monitoring is performed once per the interval determined by Reg_0x69[3:0].
		6:0	0000000	N		Reserved
0x3F	00	7	0	Y	R/W	Reserved
		6:0	0000000	N
0x40 - 0x4F				Y	R/W	CTLE Settings for Adaptation Table 23
0x50	00	7	0	N	R/W	Reserved
		6	0	Y		Reserved
		5	0	N		Reserved
		4	0	Y		Slicer Sign Bit
		3:0	0000	Y		Slicer adjustment in 5mV steps. Maximum adjustment value is 50mV or 0x50[3:0] = A’h
0x51	00	7:0	00’h	Y	R/W	Reserved
0x52	00	7:0	00’h	N	R	CTLE Boost setting readback register.
0x53	00	7:0	00’h	N	R/W	Reserved
0x54	00	7	0	N	R	Signal Detect observation bit.
		6	0			EQ Limiting (CTLE Stage 3[2]) observation bit.
		5:2	0000			Reserved
		1	0			CDR Lock Interrupt
		0	0			Signal Detect Interrupt
0x55	00	7	0	N	R/W	Reserved
		6:5	00	Y		Reserved
		4	0	N		Allows observation of the alternate HEO/VEO Figure of Merit In Reg_0x27 and Reg_0X28
		3:1	0	Y		Reserved
		0	0	Y		Enables Adaption in the lower divide ratios
0x56	00	7:4	0000	N	R/W	Reserved
		3	0	Y		CDR Lock. Sticky Bit. Clears when read
		2	0	Y		Signal Acquired. Sticky Bit. Clears when read
		1	0	Y		CDR loss of Lock. Sticky Bit. Clears when read
		0	0	Y		Loss of Signal. Sticky Bit. Clears when read
0x60	00	7:0	00’h	Y	R/W	Group 0 (Rate/Subrate defined) PPM counter <7:0> LSBs
0x61	00	7	0	Y	R/W	Override standard Group 0 tie cells for PPM count and tolerance with Channel Registers 0x60, 0x61, and 0x64
		6:0	000 0000			Group 0 (Rate/Subrate defined) PPM counter <14:8> MSBs
0x62	00	7:0	00’h	Y	R/W	Group 1 (Rate/Subrate defined) PPM counter <7:0> LSBs
0x63	00	7	0	Y	R/W	Override standard Group 1 tie cells for PPM count and tolerance with Channel Registers 0x62, 0x63, and 0x64
		6:0	000 0000			Group 1 (Rate/Subrate defined) PPM counter <14:8> MSBs
0x64	00	7:4	0000	Y	R/W	Group 0 PPM Delta
		3:0	0000			Group 1 PPM Delta
0x65	00	7:0	00'h	N	R/W	Reserved
0x66	00	7:0	00'h	N	R/W	Reserved
0x67	00	7:6	00	N	R/W	Reserved
		5	0	Y		Reserved
		4:0	00000	N		Reserved
0x68	00	7:0	00'h	N	R/W	Reserved
0x69	0A	7:4	0000	N	R/W	Reserved
		3:0	1010	Y		HEO/VEO interval while monitoring lock. Monitoring will take place 1 out of the indicated count intervals (default h'A). Interval time is determined 0x2B[5:4], which is 6.5ms by default.
0x6A	44	7:4	0100	N	R/W	Vertical Eye Opening Lock Threshold <3:0>
		3:0	0100			Horizontal Eye Opening Lock Threshold <3:0>
0x6B	40	7:0	40’h	Y	R/W	Adaptation Figure of Merit Term A<7:0> FoM = Min [(HEO - B)*A, (VEO - C)*(1-A)] FoM = Min [(HEO - 0x6C) * (0x6B)/127, (VEO - 0x6D) * (128 - 0x6B)/127]
0x6C	00	7:0	0x0	Y	R/W	Adaptation Figure of Merit Term B<7:0> FoM = Min [(HEO - B)*A, (VEO - C)*(1-A)] FoM = Min [(HEO - 0x6C) * (0x6B)/127, (VEO - 0x6D) * (128 - 0x6B)/127]
0x6D	00	7:0	0x0	Y	R/W	Adaptation Figure of Merit Term C<7:0> FoM = Min [(HEO - B)*A, (VEO - C)*(1-A)] FoM = Min [(HEO - 0x6C) * (0x6B)/127, (VEO - 0x6D) * (128 - 0x6B)/127]
0x6E	00	7	0	Y	R/W	Enable Alternate Figure of Merit for CTLE Adaptation
		6	0	Y		Enable Alternate Figure of Merit for DFE Adaptation
		5:0	000000	N		Reserved
0x6F	00	7:0	00'h	N	R/W	Reserved
0x70	03	7:3	00000	N	R/W	Reserved
		2:0	011			CTLE Adaptation Look-Beyond Count <2:0>
0x71	00	7:6	00	N	R/W	Reserved
		5	0		R	DFE Tap 1 Polarity (Read Only)
		4:0	0 0000		R	DFE Tap 1 Weight (Read Only) <4:0>
0x72	00	7:5	000	N	R/W	Reserved
		4	0		R	DFE Tap 2 Polarity (Read Only)
		3:0	0000		R	DFE Tap 2 Weight (Read Only) <3:0>
0x73	00	7:5	000	N	R/W	Reserved
		4	0		R	DFE Tap 3 Polarity (Read Only)
		3:0	0000		R	DFE Tap 3 Weight (Read Only) <3:0>
0x74	00	7:5	000	N	R/W	Reserved
		4	0		R	DFE Tap 4 Polarity (Read Only)
		3:0	0000		R	DFE Tap 4 Weight (Read Only) <3:0>
0x75	00	7:5	000	N	R/W	Reserved
		4	0		R	DFE Tap 5 Polarity (Read Only)
		3:0	0000		R	DFE Tap 5 Weight (Read Only) <3:0>