SNLS396D January 2012 – January 2016 DS100MB203
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- NJY|54
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7 Detailed Description
7.1 Overview
The DS100MB203 is a dual lane 2:1 multiplexer and 1:2 switch or fan-out buffer with signal conditioning. The DS100MB203 compensates for lossy FR-4 printed-circuit-board backplanes and balanced cables. The DS100MB203 operates in 3 modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1) and SMBus Master Mode (ENSMB = float) to load register information from external EEPROM; please refer to SMBUS Master Mode for additional information.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 4-Level Input Configuration Guidelines
The 4-level input pins use a resistor divider to help set the four valid control levels and provide a wider range of control settings when ENSMB = 0. There is an internal 30-kΩ pullup and a 60-kΩ pulldown connected to the package pin. These resistors, together with the external resistor connection, combine to achieve the desired voltage level. By using the 1-kΩ pulldown, 20-kΩ pulldown, no connect, and 1-kΩ pullup, the optimal voltage levels for each of the four input states are achieved as shown in Table 1.
Table 1. 4–Level Control Pin Settings
| LEVEL | SETTING | RESULTING PIN VOLTAGE | |
|---|---|---|---|
| 3.3-V MODE | 2.5-V MODE | ||
| 0 | Tie 1 kΩ to GND | 0.1 V | 0.08 V |
| R | Tie 20 kΩ to GND | 1/3 x VIN | 1/3 x VDD |
| F | Float (leave pin open) | 2/3 x VIN | 2/3 x VDD |
| 1 | Tie 1 kΩ to VIN or VDD | VIN – 0.05 V | VDD – 0.04 V |
The typical 4-Level input thresholds are as follows:
- Internal Threshold between 0 and R = 0.2 × VIN or VDD
- Internal Threshold between R and F = 0.5 × VIN or VDD
- Internal Threshold between F and 1 = 0.8 × VIN or VDD
In order to minimize the start-up current associated with the integrated 2.5-V regulator, the 1-kΩ pullup and pulldown resistors are recommended. If several four level inputs require the same setting, it is possible to combine two or more 1-kΩ resistors into a single lower value resistor. As an example, combining two inputs with a single 500-Ω resistor is a valid way to save board space.
7.4 Device Functional Modes
7.4.1 Pin Control Mode
When in pin mode (ENSMB = 0) , the repeater is configurable with external pins. Equalization and de-emphasis can be selected through pin for each side independently. When de-emphasis is asserted VOD is automatically adjusted per Table 3. The receiver electrical idle detect threshold is also adjustable via the SD_TH pin.
7.4.2 SMBUS Mode
When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode case. Upon assertion of ENSMB the MODE, EQx and DEMx functions revert to register control immediately. The EQx and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins remain active unless their respective registers are written to and the appropriate override bit is set, in which case they are ignored until ENSMB is driven low (pin mode). On power up and when ENSMB is driven low all registers are reset to their default state. If RESET is asserted while ENSMB is high, the registers retain their current state.
Equalization settings accessible through the pin controls were chosen to meet the needs of most applications. If additional fine tuning or adjustment is needed, additional equalization settings can be accessed through the SMBus registers. Each input has a total of 256 possible equalization settings. The tables show the 16 setting when the device is in pin mode. When using SMBus mode, the equalization, VOD and de-Emphasis levels are set by registers.
The input control pins have been enhanced to have 4 different levels and provide a wider range of control settings when ENSMB=0.
Table 2. Equalizer Settings
| LEVEL | EQ_D1 EQ_S1 |
EQ_D0 EQ_S0 |
EQ – 8 BITS [7:0] | dB AT 1.25 GHz |
dB AT 2.5 GHz |
dB AT 4 GHz |
dB AT 5 GHz |
SUGGESTED USE(1) |
|---|---|---|---|---|---|---|---|---|
| 1 | 0 | 0 | 0000 0000 = 0x00 | 2.1 | 3.7 | 4.9 | 5.3 | FR4 < 5 inch trace |
| 2 | 0 | R | 0000 0001 = 0x01 | 3.4 | 5.8 | 7.9 | 8.7 | FR4 5 inch 5–mil trace |
| 3 | 0 | Float | 0000 0010 = 0x02 | 4.8 | 7.7 | 9.9 | 10.6 | FR4 5 inch 4–mil trace |
| 4 | 0 | 1 | 0000 0011 = 0x03 | 5.9 | 8.9 | 11.0 | 11.7 | FR4 10 inch 5–mil trace |
| 5 | R | 0 | 0000 0111 = 0x07 | 7.2 | 11.2 | 14.3 | 15.6 | FR4 10 inch 4–mil trace |
| 6 | R | R | 0001 0101 = 0x15 | 6.1 | 11.4 | 14.6 | 16.6 | FR4 15 inch 4–mil trace |
| 7 | R | Float | 0000 1011 = 0x0B | 8.8 | 13.5 | 17.0 | 18.3 | FR4 20 inch 4–mil trace |
| 8 | R | 1 | 0000 1111 = 0x0F | 10.2 | 15.0 | 18.5 | 19.7 | FR4 25 to 30 inch 4–mil trace |
| 9 | Float | 0 | 0101 0101 = 0x55 | 7.5 | 12.8 | 18.0 | 20.3 | FR4 30 inch 4–mil trace |
| 10 | Float | R | 0001 1111 = 0x1F | 11.4 | 17.4 | 22.0 | 23.6 | FR4 35 inch 4–mil trace |
| 11 | Float | Float | 0010 1111 = 0x2F | 13.0 | 19.7 | 24.4 | 25.8 | 10-m, 30-awg cable |
| 12 | Float | 1 | 0011 1111 = 0x3F | 14.2 | 21.1 | 25.8 | 27.0 | 10-m – 12-m cable |
| 13 | 1 | 0 | 1010 1010 = 0xAA | 13.8 | 21.7 | 27.4 | 29.1 | |
| 14 | 1 | R | 0111 1111 = 0x7F | 15.6 | 23.5 | 29.0 | 30.7 | |
| 15 | 1 | Float | 1011 1111 = 0xBF | 17.2 | 25.8 | 31.4 | 32.7 | |
| 16 | 1 | 1 | 1111 1111 = 0xFF | 18.4 | 27.3 | 32.7 | 33.8 |
(1) FR4 lengths are for reference only. FR4 lengths based on a 100-Ω differential stripline with 5-mil traces and 8-mil trace separation.
Table 3. De-Emphasis and Output Voltage Settings
| LEVEL | DEM_D1 DEM_S1 |
DEM_D0 DEM_S0 |
VOD Vp-p | DEM dB | INNER AMPLITUDE Vp-p | SUGGESTED USE(1) |
|---|---|---|---|---|---|---|
| 1 | 0 | 0 | 0.6 | 0 | 0.6 | FR4 <5 inch 4–mil trace |
| 2 | 0 | R | 0.8 | 0 | 0.8 | FR4 <5 inch 4–mil trace |
| 3 | 0 | Float | 0.8 | –3.5 | 0.55 | FR4 10 inch 4–mil trace |
| 4 | 0 | 1 | 0.9 | 0 | 1.0 | FR4 <5 inch 4–mil trace |
| 5 | R | 0 | 0.9 | –3.5 | 0.45 | FR4 10 inch 4–mil trace |
| 6 | R | R | 0.9 | –6 | 0.5 | FR4 15 inch 4–mil trace |
| 7 | R | Float | 1.0 | 0 | 1.0 | FR4 <5 inch 4–mil trace |
| 8 | R | 1 | 1.0 | –3.5 | 0.7 | FR4 10 inch 4–mil trace |
| 9 | Float | 0 | 1.0 | –6 | 0.5 | FR4 15 inch 4–mil trace |
| 10 | Float | R | 1.1 | 0 | 1.1 | FR4 <5 inch 4–mil trace |
| 11 | Float | Float | 1.1 | –3.5 | 0.7 | FR4 10 inch 4–mil trace |
| 12 | Float | 1 | 1.1 | –6 | 0.55 | FR4 15 inch 4–mil trace |
| 13 | 1 | 0 | 1.2 | 0 | 1.2 | FR4 <5 inch 4–mil trace |
| 14 | 1 | R | 1.2 | –3.5 | 0.8 | FR4 10 inch 4–mil trace |
| 15 | 1 | Float | 1.2 | –6 | 0.6 | FR4 15 inch 4–mil trace |
| 16 | 1 | 1 | 1.2 | –9 | 0.45 | FR4 20 inch 4–mil trace |
(1) The VOD output amplitude and DEM de-emphasis levels are set with the DEMD/S[1:0] pins.
Table 4. Input Termination Condition with RESET, INPUT_EN and SEL0 / SEL1
| RESET | INPUT_EN | SEL0 SEL1 |
MODE | INPUT_TERM S_INA0, S_INA1 |
INPUT_TERM S_INB0, S_INB1 |
INPUT_TERM D_IN0, D_IN1 |
|---|---|---|---|---|---|---|
| 1 | X | X | Low Power | High Z | High Z | High Z |
| 0 | 0 | X | Manual Mux Mode | 50 Ω | 50 Ω | 50 Ω |
| 0 | R | X | Reserved | Reserved | Reserved | Reserved |
| 0 | F | 0 | Auto - continuous poll, DIN_B | High Z | Auto RX-Detect, output tests every 12 msec until detection occurs, input termination is high-z until detection; once detected input termination is 50 Ω | Auto RX-Detect, output tests every 12 msec until detection occurs, input termination is high-z until detection; once detected input termination is 50 Ω |
| 0 | F | R | Auto - continuous poll, DIN_B | High Z | Auto RX-Detect, output tests every 12 msec until detection occurs, input termination is high-z until detection; once detected input termination is 50 Ω | Auto RX-Detect, output tests every 12 msec until detection occurs, input termination is high-z until detection; once detected input termination is 50 Ω |
| 0 | F | F | Auto - continuous poll, DIN_A | Auto RX-Detect, output tests every 12 msec until detection occurs, input termination is high-z until detection; once detected input termination is 50 Ω | High Z | Auto RX-Detect, output tests every 12 msec until detection occurs, input termination is high-z until detection; once detected input termination is 50 Ω |
| 0 | F | 1 | Auto - continuous poll, DIN_A | Auto RX-Detect, output tests every 12 msec until detection occurs, input termination is high-z until detection; once detected input termination is 50 Ω | High Z | Auto RX-Detect, output tests every 12 msec until detection occurs, input termination is high-z until detection; once detected input termination is 50 Ω |
| 0 | 1 | X | Manual Fanout Mode | 50 Ω | 50 Ω | 50 Ω |
Table 5. Mux/Switch and FANOUT Control
| SEL0 | SEL1 | INPUT_EN | DESCRIPTION OF CONNECTION PATH |
|---|---|---|---|
| 0 | 0 | 0 | D_OUT0 connects to S_INB0. D_OUT1 connects to S_INB1. D_IN0 connects to S_OUTB0. S_OUTA0 is in IDLE (output muted). D_IN1 connects to S_OUTB1. S_OUTA1 is in IDLE (output muted). |
| 0 | 0 | R | Reserved |
| 0 | 0 | F | D_OUT0 connects to S_INB0. D_OUT1 connects to S_INB1. D_IN0 connects to S_OUTB0. S_OUTA0 is in IDLE (output muted). D_IN1 connects to S_OUTB1. S_OUTA1 is in IDLE (output muted). |
| 0 | 0 | 1 | D_OUT0 connects to S_INB0. D_OUT1 connects to S_INB1. D_IN0 connects to S_OUTB0 and S_OUTA0. D_IN1 connects to S_OUTB1 and S_OUTA1. |
| R | R | 0 | D_OUT0 connects to S_INB0. D_OUT1 connects to S_INB1. D_IN0 connects to S_OUTA0. S_OUTB0 is in IDLE (output muted). D_IN1 connects to S_OUTA1. S_OUTB1 is in IDLE (output muted). |
| R | R | R | Reserved |
| R | R | F | D_OUT0 connects to S_INB0. D_OUT1 connects to S_INB1. D_IN0 connects to S_OUTA0. S_OUTB0 is in IDLE (output muted). D_IN1 connects to S_OUTA1. S_OUTB1 is in IDLE (output muted). |
| R | R | 1 | D_OUT0 connects to S_INB0. D_OUT1 connects to S_INB1. D_IN0 connects to S_OUTB0 and S_OUTA0. D_IN1 connects to S_OUTB1 and S_OUTA1. |
| F | F | 0 | D_OUT0 connects to S_INA0. D_OUT1 connects to S_INA1. D_IN0 connects to S_OUTB0. S_OUTA0 is in IDLE (output muted). D_IN1 connects to S_OUTB1. S_OUTA1 is in IDLE (output muted). |
| F | F | R | Reserved |
| F | F | F | D_OUT0 connects to S_INA0. D_OUT1 connects to S_INA1. D_IN0 connects to S_OUTB0. S_OUTA0 is in IDLE (output muted). D_IN1 connects to S_OUTB1. S_OUTA1 is in IDLE (output muted). |
| F | F | 1 | D_OUT0 connects to S_INA0. D_OUT1 connects to S_INA1. D_IN0 connects to S_OUTB0 and S_OUTA0. D_IN1 connects to S_OUTB1 and S_OUTA1. |
| 1 | 1 | 0 | D_OUT0 connects to S_INA0. D_OUT1 connects to S_INA1. D_IN0 connects to S_OUTA0. S_OUTB0 is in IDLE (output muted). D_IN1 connects to S_OUTA1. S_OUTB1 is in IDLE (output muted). |
| 1 | 1 | R | Reserved |
| 1 | 1 | F | D_OUT0 connects to S_INA0. D_OUT1 connects to S_INA1. D_IN0 connects to S_OUTA0. S_OUTB0 is in IDLE (output muted). D_IN1 connects to S_OUTA1. S_OUTB1 is in IDLE (output muted). |
| 1 | 1 | 1 | D_OUT0 connects to S_INA0. D_OUT1 connects to S_INA1. D_IN0 connects to S_OUTA0 and S_OUTB0. D_IN1 connects to S_OUTA1 and S_OUTB1. |
7.5 Programming
7.5.1 SMBUS Master Mode
The DS100MB203 devices support reading directly from an external EEPROM device by implementing SMBus Master mode. When using the SMBus master mode, the DS100MB203 will read directly from specific location in the external EEPROM. When designing a system for using the external EEPROM, the user needs to follow these specific guidelines below.
NOTE
SEL0, SEL1 and INPUT_EN control are to be set with the external strap pins because there are no register bits to configure them.
- Set ENSMB = Float – enable the SMBUS master mode.
- The external EEPROM device address byte must be 0xA0'h and capable of 1-MHz operation at 2.5-V and 3.3-V supply. The maximum allowed size is 8 kbits (1024 bytes).
- Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is B0'h.
When tying multiple DS100MB203 devices to the SDA and SCL bus, use these guidelines to configure the devices.
- Use SMBus AD[3:0] address bits so that each device can loaded its configuration from the EEPROM. Example below is for 4 device.
U1: AD[3:0] = 0000 = 0xB0'h,
U2: AD[3:0] = 0001 = 0xB2'h,
U3: AD[3:0] = 0010 = 0xB4'h,
U4: AD[3:0] = 0011 = 0xB6'h - Use a pull-up resistor on SDA and SCL; value = 2 kΩ
- Daisy-chain READEN# (pin 26) and ALL_DONE# (pin 27) from one device to the next device in the sequence so that they do not compete for the EEPROM at the same time.
1. Tie READEN# of the 1st device in the chain (U1) to GND
2. Tie ALL_DONE# of U1 to READEN# of U2
3. Tie ALL_DONE# of U2 to READEN# of U3
4. Tie ALL_DONE# of U3 to READEN# of U4
5. Optional: Tie ALL_DONE# output of U4 to a LED to show the devices have been loaded successfully
Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS100MB203 device. The first 3 bytes of the EEPROM always contain a header common and necessary to control initialization of all devices connected to the I2C bus. CRC enable flag to enable/disable CRC checking. If CRC checking is disabled, a fixed pattern (8’hA5) is written/read instead of the CRC byte from the CRC location, to simplify the control. There is a MAP bit to flag the presence of an address map that specifies the configuration data start in the EEPROM. If the MAP bit is not present the configuration data start address is derived from the DS100MB203 address and the configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the EEPROM. There are 37 bytes of data size for each DS100MB203 device.
:2000000000001000000407002FAD4002FAD4002FAD4002FAD409805F5A8005F5A8005F5AD0
:200020008005F5A800005454000000000000000000000000000000000000000000000000F6
:20006000000000000000000000000000000000000000000000000000000000000000000080
:20008000000000000000000000000000000000000000000000000000000000000000000060
:2000A000000000000000000000000000000000000000000000000000000000000000000040
:2000C000000000000000000000000000000000000000000000000000000000000000000020
:2000E000000000000000000000000000000000000000000000000000000000000000000000
:200040000000000000000000000000000000000000000000000000000000000000000000A0
NOTE
The maximum EEPROM size supported is 8 kbits (1024 × 8 bits). For more information in regards to EEPROM programming and the hex format, see SNLA228.
7.6 Register Maps
7.6.1 System Management Bus (SMBus) and Configuration Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB = 1 kΩ to VDD to enable SMBus slave mode and allow access to the configuration registers.
The DS100MB203 has the AD[3:0] inputs in SMBus mode. These pins are the user set SMBUS slave address inputs. The AD[3:0] pins have internal pulldown. When left floating or pulled low the AD[3:0] = 0000'b, the device default address byte is B0'h. Based on the SMBus 2.0 specification, the DS100MB203 has a 7-bit slave address. The LSB is set to 0'b (for a WRITE). The device supports up to 16 address bytes, which can be set with the AD[3:0] inputs. Below are the 16 addresses.
Table 6. Device Slave Address Bytes
| AD[3:0] SETTINGS | ADDRESS BYTES (HEX) |
|---|---|
| 0000 | B0 |
| 0001 | B2 |
| 0010 | B4 |
| 0011 | B6 |
| 0100 | B8 |
| 0101 | BA |
| 0110 | BC |
| 0111 | BE |
| 1000 | C0 |
| 1001 | C2 |
| 1010 | C4 |
| 1011 | C6 |
| 1100 | C8 |
| 1101 | CA |
| 1110 | CC |
| 1111 | CE |
The SDA, SCL pins are 3.3-V tolerant, but are not 5-V tolerant. External pullup resistor is required on the SDA. The resistor value can be from 1 kΩ to 5 kΩ depending on the voltage, loading and speed. The SCL may also require an external pullup resistor and it depends on the Host that drives the bus.
7.6.1.1 Transfer of Data Through the SMBus
During normal operation the data on SDA must be stable during the time when SCL is high.
There are three unique states for the SMBus:
- START: A high-to-low transition on SDA while SCL is high indicates a message START condition.
- STOP: A low-to-high transition on SDA while SCL is high indicates a message STOP condition.
-
IDLE: If SCL and SDA are both high for a time exceeding tBUF from the last detected STOP condition or if they are high for a total exceeding the maximum specification for tHIGH then the bus will transfer
to the IDLE state.
7.6.1.2 SMBus Transactions
The device supports WRITE and READ transactions. See Table 8 for register address, type (Read/Write, Read Only), default value and function information.
7.6.1.3 Writing a Register
To write a register, the following protocol is used (see SMBus 2.0 specification).
- The host drives a START condition, the 7-bit SMBus address, and a 0 indicating a WRITE.
- The device (slave) drives the ACK bit (0).
- The host drives the 8-bit register address.
- The device drives an ACK bit (0).
- The host drive the 8-bit data byte.
- The device drives an ACK bit (0).
- The host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices
may now occur.
7.6.1.4 Reading a Register
To read a register, the following protocol is used (see SMBus 2.0 specification).
- The host drives a START condition, the 7-bit SMBus address, and a 0 indicating a WRITE.
- The device (Slave) drives the ACK bit (0).
- The host drives the 8-bit register address.
- The device drives an ACK bit (0).
- The host drives a START condition.
- The host drives the 7-bit SMBus Address, and a 1 indicating a READ.
- The device drives an ACK bit 0.
- The device drives the 8-bit data value (register contents).
- The host drives a NACK bit 1 indicating end of the READ transfer.
- The host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices
may now occur.
Please see Table 7 for more information.
Table 7. SMBUS Slave Mode Register Map
| ADDRESS | REGISTER NAME |
BIT | FIELD | TYPE | DEFAULT | EEPROM REG BIT |
DESCRIPTION |
|---|---|---|---|---|---|---|---|
| 0x00 | Observation | 7 | Reserved | R/W | 0x00 | Set bit to 0 | |
| 6:3 | Address Bit AD[3:0] |
R | Observation of AD[3:0] bits [6]: AD3 [5]: AD2 [4]: AD1 [3]: AD0 |
||||
| 2 | EEPROM Read Done | R | 1 = Device completed the read from external EEPROM | ||||
| 1 | Block Reset | R/W | 1: Block bit 0 from resetting the registers; self clearing. | ||||
| 0 | Reset | R/W | SMBus reset 1: Reset registers to default value; self clearing. |
||||
| 0x01 | PWDN Channels | 7:0 | PWDN CHx | R/W | 0x00 | Yes | Power down per channel [7]: CH7 (NC – S_OUTB1) [6]: CH6 (D_IN1 – S_OUTA1) [5]: CH5 (NC – S_OUTB0) [4]: CH4 (D_IN0 – S_OUTA0) [3]: CH3 (D_OUT1 – S_INB1) [2]: CH2 (NC – S_INA1) [1]: CH1 (D_OUT0 – S_INB0) [0]: CH0 (NC – S_INA0) 0x00 = all channels enabled 0xFF = all channels disabled Note: Override PWDN pin and enable register control through Reg 0x02[0] |
| 0x02 | Override RESET Control | 7 | Reserved | R/W | 0x00 | Set bit to 0 | |
| 6 | Reserved | Set bit to 0 | |||||
| 5:2 | Reserved | Yes | Set bits to 0 | ||||
| 1 | Reserved | Set bit to 0 | |||||
| 0 | Override RESET | Yes | 1: Block RESET pin control; use Reg_01 to configure. 0: Allow RESET pin control. |
||||
| 0x03 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x04 | Reserved | 7:0 | Reserved | R/W | 0x00 | Yes | Set bits to 0 |
| 0x05 | Reserved | 7:0 | Reserved | R/W | 0x00 | Reserved | |
| 0x06 | Slave Register Control | 7:5 | Reserved | R/W | 0x10 | Set bits to 0 | |
| 4 | Reserved | Yes | Set bit to 1 | ||||
| 3 | Register Enable | 1 = Enable SMBus slave mode register control 0 = Disable SMBus register control Note: In order to change VOD, DEM, and EQ of the channels in slave mode, this bit must be set to 1. |
|||||
| 2:0 | Reserved | Set bits to 0 | |||||
| 0x07 | Reserved | 7:1 | Reserved | R/W | 0x01 | Set bits to 0 | |
| 0 | Reserved | Set bit to 1 | |||||
| 0x08 | Override Pin Control |
7 | Reserved | R/W | 0x00 | Set bit to 0 | |
| 6:4 | Reserved | Yes | Set bits to 0 | ||||
| 3 | Override RXDET | Yes | 1 = Block RXDET pin control (register control enabled) 0 = Allow RXDET pin control (register control disabled) |
||||
| 2 | Override MODE | Yes | 1: Block MODE pin control; use register to configure. 0: Allow MODE pin control |
||||
| 1:0 | Reserved | Yes | Set bits to 0 | ||||
| 0x09 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x0A | Reserved | 7:0 | Reserved | R | 0x00 | ||
| 0x0B | Reserved | 7 | Reserved | R/W | 0x70 | Set bit to 0 | |
| 6:0 | Reserved | R/W | Yes | Set bits to 111 0000'b | |||
| 0x0C-0x0D | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x0E | CH0 NC – S_INA0 RXDET |
7:6 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 5:4 | Reserved | Yes | Set bits to 0 | ||||
| 3:2 | RXDET | Yes | 00'b = Input is Hi-Z impedance 01'b = Auto Rx-Detect, outputs test every 12 ms for 600 ms (50 times) then stops; termination is Hi-Z until detection; once detected input termination is 50 Ω 10'b = Auto Rx-Detect, outputs test every 12 ms until detection occurs; termination is Hi-Z until detection; once detected input termination is 50 Ω 11'b = Input is 50 Ω Note: Override RXDET pin and enable register control via Reg 0x08[3] |
||||
| 1:0 | Reserved | Set bits to 0 | |||||
| 0x0F | CH0 NC – S_INA0 EQ |
7:0 | EQ Control | R/W | 0x2F | Yes | EQ Control - total of 256 levels. See Table 2. |
| 0x10 | Reserved | 7:0 | Reserved | R/W | 0xAD | Yes | |
| 0x11 | CH0 NC – S_INA0 Reserved |
7:3 | Reserved | R/W | 0x02 | Set bits to 0 | |
| 2:0 | Reserved | Yes | |||||
| 0x12 | CH0 NC – S_INA0 Reserved |
7 | Reserved | R/W | 0x00 | Yes | Set bit to 0 |
| 6:4 | Reserved | Set bits to 0 | |||||
| 3:2 | Reserved | Yes | Set bits to 0 | ||||
| 1:0 | Reserved | Yes | Set bits to 0 | ||||
| 0x13-0x14 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x15 | CH1 D_OUT0 – S_INB0 RXDET |
7:6 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 5:4 | Reserved | Yes | Set bits to 0 | ||||
| 3:2 | RXDET | Yes | 00'b = Input is Hi-Z impedance 01'b = Auto Rx-Detect, outputs test every 12 ms for 600 ms (50 times) then stops; termination is Hi-Z until detection; once detected input termination is 50 Ω 10'b = Auto Rx-Detect, outputs test every 12 ms until detection occurs; termination is Hi-Z until detection; once detected input termination is 50 Ω 11'b = Input is 50 Ω Note: Override RXDET pin and enable register control through Reg 0x08[3] |
||||
| 1:0 | Reserved | Set bits to 0 | |||||
| 0x16 | CH1 D_OUT0 – S_INB0 EQ |
7:0 | EQ Control | R/W | 0x2F | Yes | EQ Control - total of 256 levels. See Table 2. |
| 0x17 | CH1 D_OUT0 – S_INB0 VOD |
7 | Short Circuit Protection | R/W | 0xAD | Yes | 1 = Enable the short circuit protection 0 = Disable the short circuit protection |
| 6 | MODE Control | Yes | 1 = PCIe GEN 1/2, 10GE 0 = PCIe GEN 3, 10G-KR Note: Override the MODE pin in Reg_08. |
||||
| 5:3 | Reserved | Yes | Set bits to 101'b | ||||
| 2:0 | VOD Control | Yes | VOD Control: 000'b = 0.6 V 001'b = 0.7 V 010'b = 0.8 V 011'b = 0.9 V 100'b = 1.0 V 101'b = 1.1 (default) 110'b = 1.2 111'b = 1.3 |
||||
| 0x18 | CH1 D_OUT0 – S_INB0 DEM |
7 | RXDET Status | R | 0x02 | Observation bit for RXDET CH1 1 = Input 50 Ω terminated to VDD 0 = Input is Hi-Z |
|
| 6:5 | Reserved | Set bits to 0 | |||||
| 4:3 | Reserved | R/W | Set bits to 0 | ||||
| 2:0 | DEM Control | Yes | DEM Control 000'b = 0 dB 001'b = –1.5 dB 010'b = –3.5 dB (default) 011'b = –5 dB 100'b = –6 dB 101'b = –8 dB 110'b = –9 dB 111'b = –12 dB |
||||
| 0x19 | CH1 D_OUT0 – S_INB0 Reserved |
7 | Reserved | R/W | 0x00 | Yes | Set bit to 0 |
| 6:4 | Reserved | Set bits to 0 | |||||
| 3:2 | Reserved | Yes | Set bits to 0 | ||||
| 1:0 | Reserved | Yes | Set bits to 0 | ||||
| 0x1A-0x1B | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x1C | CH2 NC – S_INA1 RXDET |
7:6 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 5:4 | Reserved | Yes | Set bits to 0 | ||||
| 3:2 | RXDET | Yes | 00'b = Input is Hi-Z impedance 01'b = Auto Rx-Detect, outputs test every 12 ms for 600 ms (50 times) then stops; termination is Hi-Z until detection; once detected input termination is 50 Ω 10'b = Auto Rx-Detect, outputs test every 12 ms until detection occurs; termination is Hi-Z until detection; once detected input termination is 50 Ω 11'b = Input is 50 Ω Note: Override RXDET pin and enable register control through Reg 0x08[3] |
||||
| 1:0 | Reserved | Set bits to 0 | |||||
| 0x1D | CH2 NC – S_INA1 EQ |
7:0 | EQ Control | R/W | 0x2F | Yes | EQ Control - total of 256 levels. See Table 2. |
| 0x1E | Reserved | 7:0 | Reserved | R/W | 0xAD | Yes | |
| 0x1F | Reserved | 7:3 | Reserved | R/W | 0x02 | ||
| 2:0 | Yes | ||||||
| 0x20 | CH2 NC – S_INA1 Reserved |
7 | Reserved | R/W | 0x00 | Yes | Set bit to 0 |
| 6:4 | Reserved | Set bits to 0 | |||||
| 3:2 | Reserved | Yes | Set bits to 0 | ||||
| 1:0 | Reserved | Yes | Set bits to 0 | ||||
| 0x21-0x22 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x23 | CH3 D_OUT1 – S_INB1 RXDET |
7:6 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 5:4 | Reserved | Yes | Set bits to 0 | ||||
| 3:2 | RXDET | Yes | 00'b = Input is Hi-Z impedance 01'b = Auto Rx-Detect, outputs test every 12 ms for 600 ms (50 times) then stops; termination is Hi-Z until detection; once detected input termination is 50 Ω 10'b = Auto Rx-Detect, outputs test every 12 ms until detection occurs; termination is Hi-Z until detection; once detected input termination is 50 Ω 11'b = Input is 50 Ω Note: Override RXDET pin and enable register control through Reg 0x08[3] |
||||
| 1:0 | Reserved | Set bits to 0 | |||||
| 0x24 | CH3 D_OUT1 – S_INB1 EQ |
7:0 | EQ Control | R/W | 0x2F | Yes | EQ Control - total of 256 levels. See Table 2. |
| 0x25 | CH3 D_OUT1 – S_INB1 VOD |
7 | Short Circuit Protection | R/W | 0xAD | Yes | 1 = Enable the short circuit protection 0 = Disable the short circuit protection |
| 6 | MODE Control | Yes | 1 = PCIe GEN 1/2, 10GE 0 = PCIe GEN 3, 10G-KR Note: override the MODE pin in Reg_08. |
||||
| 5:3 | Reserved | Yes | Set bits to 101'b | ||||
| 2:0 | VOD Control | Yes | VOD Control: 000'b = 0.6 V 001'b = 0.7 V 010'b = 0.8 V 011'b = 0.9 V 100'b = 1.0 V 101'b = 1.1 (default) 110'b = 1.2 111'b = 1.3 |
||||
| 0x26 | CH3 D_OUT1 – S_INB1 DEM |
7 | RXDET Status | R | 0x02 | Observation bit for RXDET CH3 - CHB_3 1 = Input 50 Ω terminated to VDD 0 = Input is Hi-Z |
|
| 6:5 | Reserved | Set bits to 0 | |||||
| 4:3 | Reserved | R/W | Set bits to 0 | ||||
| 2:0 | DEM Control | Yes | DEM Control 000'b = 0 dB 001'b = –1.5 dB 010'b = –3.5 dB (default) 011'b = –5 dB 100'b = –6 dB 101'b = –8 dB 110'b = –9 dB 111'b = –12 dB |
||||
| 0x27 | CH3 D_OUT1 – S_INB1 Reserved |
7 | Reserved | R/W | 0x00 | Yes | Set bit to 0 |
| 6:4 | Reserved | Set bits to 0 | |||||
| 3:2 | Reserved | Yes | Set bits to 0 | ||||
| 1:0 | Reserved | Yes | Set bits to 0 | ||||
| 0x28 | Signal Detect Status Control | 7 | Reserved | R/W | 0x0C | Set bit to 0 | |
| 6 | Reserved | Yes | Set bit to 0 | ||||
| 5:4 | High SD_TH Status | Yes | Enable higher range of signal detect status thresholds [5]: CH0 - CH3 [4]: CH4 - CH7 |
||||
| 3:2 | Fast Signal Detect Status | Yes | Enable fast signal detect status [3]: CH0 - CH3 [2]: CH4 - CH7 Note: In fast signal detect, assert/de-assert response occurs after approximately 3-4 ns |
||||
| 1:0 | Reduced SD Status Gain | Yes | Enable reduced signal detect status gain [1]: CH0 - CH3 [0]: CH4 - CH7 |
||||
| 0x29-0x2A | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x2B | CH4 D_IN0 – S_OUTA0 RXDET |
7:6 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 5:4 | Reserved | Yes | Set bits to 0 | ||||
| 3:2 | RXDET | Yes | 00'b = Input is Hi-Z impedance 01'b = Auto Rx-Detect, outputs test every 12 ms for 600 ms (50 times) then stops; termination is Hi-Z until detection; once detected input termination is 50 Ω 10'b = Auto Rx-Detect, outputs test every 12 ms until detection occurs; termination is Hi-Z until detection; once detected input termination is 50 Ω 11'b = Input is 50 Ω Note: Override RXDET pin and enable register control through Reg 0x08[3] |
||||
| 1:0 | Reserved | Set bits to 0 | |||||
| 0x2C | CH4 D_IN0 – S_OUTA0 EQ |
7:0 | EQ Control | R/W | 0x2F | Yes | EQ Control - total of 256 levels. See Table 2. |
| 0x2D | CH4 D_IN0 – S_OUTA0 VOD |
7 | Short Circuit Protection | R/W | 0xAD | Yes | 1 = Enable the short circuit protection 0 = Disable the short circuit protection |
| 6 | MODE Control | Yes | 1 = PCIe GEN 1/2, 10GE 0 = PCIe GEN 3, 10G-KR Note: override the MODE pin in Reg_08. |
||||
| 5:3 | Reserved | Yes | Set bits to 101'b | ||||
| 2:0 | VOD Control | Yes | VOD Control: 000'b = 0.6 V 001'b = 0.7 V 010'b = 0.8 V 011'b = 0.9 V 100'b = 1.0 V 101'b = 1.1 (default) 110'b = 1.2 111'b = 1.3 |
||||
| 0x2E | CH4 D_IN0 – S_OUTA0 DEM |
7 | RXDET Status | R | 0x02 | Observation bit for RXDET CH4 - CHA_0 1 = Input 50 Ω terminated to VDD 0 = Input is Hi-Z |
|
| 6:5 | Reserved | Set bits to 0 | |||||
| 4:3 | Reserved | R/W | Set bits to 0 | ||||
| 2:0 | DEM Control | Yes | DEM Control 000'b = 0 dB 001'b = –1.5 dB 010'b = –3.5 dB (default) 011'b = –5 dB 100'b = –6 dB 101'b = –8 dB 110'b = –9 dB 111'b = –12 dB |
||||
| 0x2F | CH4 D_IN0 – S_OUTA0 Reserved |
7 | Reserved | R/W | 0x00 | Yes | Set bit to 0 |
| 6:4 | Reserved | Set bits to 0 | |||||
| 3:2 | Reserved | Yes | Set bits to 0 | ||||
| 1:0 | Reserved | Yes | Set bits to 0 | ||||
| 0x30-0x31 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x32 | Reserved | 7:6 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 5:4 | Reserved | Yes | Set bits to 0 | ||||
| 3:2 | Reserved | Yes | Set bits to 0 | ||||
| 1:0 | Reserved | Set bits to 0 | |||||
| 0x33 | CH5 NC – S_OUTB0 Reserved |
7:0 | Reserved | R/W | 0x2F | Yes | |
| 0x34 | CH5 NC – S_OUTB0 VOD |
7 | Short Circuit Protection | R/W | 0xAD | Yes | 1 = Enable the short circuit protection 0 = Disable the short circuit protection |
| 6 | MODE Control | Yes | 1 = PCIe GEN 1/2, 10GE 0 = PCIe GEN 3, 10G-KR Note: Override the MODE pin in Reg_08. |
||||
| 5:3 | Reserved | Yes | Set bits to 101'b | ||||
| 2:0 | VOD Control | Yes | VOD Control: 000'b = 0.6 V 001'b = 0.7 V 010'b = 0.8 V 011'b = 0.9 V 100'b = 1.0 V 101'b = 1.1 (default) 110'b = 1.2 111'b = 1.3 |
||||
| 0x35 | CH5 NC – S_OUTB0 DEM |
7 | RXDET Status | R | 0x02 | Observation bit for RXDET CH5 - CHA1 1 = Input 50 Ω terminated to VDD 0 = Input is Hi-Z |
|
| 6:5 | Reserved | Set bits to 0 | |||||
| 4:3 | Reserved | R/W | Set bits to 0 | ||||
| 2:0 | DEM Control | Yes | DEM Control 000'b = 0 dB 001'b = –1.5 dB 010'b = –3.5 dB (default) 011'b = –5 dB 100'b = –6 dB 101'b = –8 dB 110'b = –9 dB 111'b = –12 dB |
||||
| 0x36 | CH5 NC – S_OUTB0 Reserved |
7 | Reserved | R/W | 0x00 | Yes | Set bit to 0 |
| 6:4 | Reserved | Set bits to 0 | |||||
| 3:2 | Reserved | Yes | Set bits to 0 | ||||
| 1:0 | Reserved | Yes | Set bits to 0 | ||||
| 0x37-0x38 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x39 | CH6 D_IN1 – S_OUTA1 RXDET |
7:6 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 5:4 | Reserved | Yes | Set bits to 0 | ||||
| 3:2 | RXDET | Yes | 00'b = Input is Hi-Z impedance 01'b = Auto Rx-Detect, outputs test every 12 ms for 600 ms (50 times) then stops; termination is Hi-Z until detection; once detected input termination is 50 Ω 10'b = Auto Rx-Detect, outputs test every 12 ms until detection occurs; termination is Hi-Z until detection; once detected input termination is 50 Ω 11'b = Input is 50 Ω Note: Override RXDET pin and enable register control through Reg 0x08[3] |
||||
| 1:0 | Reserved | Set bits to 0 | |||||
| 0x3A | CH6 D_IN1 – S_OUTA1 EQ |
7:0 | EQ Control | R/W | 0x2F | Yes | EQ Control - total of 256 levels. See Table 2. |
| 0x3B | CH6 D_IN1 – S_OUTA1 VOD |
7 | Short Circuit Protection | R/W | 0xAD | Yes | 1 = Enable the short circuit protection 0 = Disable the short circuit protection |
| 6 | MODE Control | Yes | 1 = PCIe GEN 1/2, 10GE 0 = PCIe GEN 3, 10G-KR Note: override the MODE pin in Reg_08. |
||||
| 5:3 | Reserved | Yes | Set bits to 0101'b | ||||
| 2:0 | VOD Control | Yes | VOD Control: 000'b = 0.6 V 001'b = 0.7 V 010'b = 0.8 V 011'b = 0.9 V 100'b = 1.0 V 101'b = 1.1 (default) 110'b = 1.2 111'b = 1.3 |
||||
| 0x3C | CH6 D_IN1 – S_OUTA1 DEM |
7 | RXDET Status | R | 0x02 | Observation bit for RXDET CH6 - CHA_2 1 = Input 50 Ω terminated to VDD 0 = Input is Hi-Z |
|
| 6:5 | Reserved | Set bits to 0 | |||||
| 4:3 | Reserved | R/W | Set bits to 0 | ||||
| 2:0 | DEM Control | Yes | DEM Control 000'b = 0 dB 001'b = –1.5 dB 010'b = –3.5 dB (default) 011'b = –5 dB 100'b = –6 dB 101'b = –8 dB 110'b = –9 dB 111'b = –12 dB |
||||
| 0x3D | CH6 D_IN1 – S_OUTA1 Reserved |
7 | Reserved | R/W | 0x00 | Yes | Set bit to 0 |
| 6:4 | Reserved | Set bits to 0 | |||||
| 3:2 | Reserved | Yes | Set bits to 0 | ||||
| 1:0 | Reserved | Yes | Set bits to 0 | ||||
| 0x3E-0x3F | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x40 | Reserved | 7:6 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 5:4 | Reserved | Yes | Set bits to 0 | ||||
| 3:2 | Reserved | Yes | Set bits to 0 | ||||
| 1:0 | Reserved | Set bits to 0 | |||||
| 0x41 | CH7 NC – S_OUTB1 EQ |
7:0 | EQ Control | R/W | 0x2F | Yes | EQ Control - total of 256 levels. See Table 2. |
| 0x42 | CH7 NC – S_OUTB1 VOD |
7 | Short Circuit Protection | R/W | 0xAD | Yes | 1 = Enable the short circuit protection 0 = Disable the short circuit protection |
| 6 | MODE Control | Yes | 1 = PCIe GEN 1/2, 10GE 0 = PCIe GEN 3, 10G-KR Note: Override the MODE pin in Reg_08. |
||||
| 5:3 | Reserved | Yes | Set bits to 101'b | ||||
| 2:0 | VOD Control | Yes | VOD Control: 000'b = 0.6 V 001'b = 0.7 V 010'b = 0.8 V 011'b = 0.9 V 100'b = 1.0 V 101'b = 1.1 (default) 110'b = 1.2 111'b = 1.3 |
||||
| 0x43 | CH7 NC – S_OUTB1 DEM |
7 | RXDET Status | R | 0x02 | Observation bit for RXDET CH7 - CHA_3 1 = Input 50 Ω terminated to VDD 0 = Input is Hi-Z |
|
| 6:5 | Reserved | Set bits to 0 | |||||
| 4:3 | Reserved | R/W | Set bits to 0 | ||||
| 2:0 | DEM Control | Yes | DEM Control 000'b = 0 dB 001'b = –1.5 dB 010'b = –3.5 dB (default) 011'b = –5 dB 100'b = –6 dB 101'b = –8 dB 110'b = –9 dB 111'b = –12 dB |
||||
| 0x44 | CH7 NC – S_OUTB1 Reserved |
7 | Reserved | R/W | 0x00 | Yes | Set bit to 0. |
| 6:4 | Reserved | Set bits to 0. | |||||
| 3:2 | Reserved | Yes | Set bits to 0. | ||||
| 1:0 | Reserved | Yes | Set bits to 0. | ||||
| 0x45 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 0x46 | Reserved | 7:0 | Reserved | R/W | 0x38 | Set bits to 0x38 | |
| 0x47 | Reserved | 7:4 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 3:0 | Reserved | Yes | Set bits to 0. | ||||
| 0x48 | Reserved | 7:6 | Reserved | R/W | 0x05 | Yes | Set bits to 0. |
| 5:0 | Reserved | R/W | Set bits to 00 0101'b | ||||
| 0x49-0x4B | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 0x4C | Reserved | 7:3 | Reserved | R/W | 0x00 | Yes | Set bits to 0. |
| 2:1 | Reserved | R/W | Set bits to 0. | ||||
| 0 | Reserved | R/W | Yes | Set bits to 0. | |||
| 0x4D-0x50 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 0x51 | Device ID | 7:5 | VERSION | R | 0x46 | 010'b | |
| 4:0 | ID | 0 0110'b | |||||
| 0x52-0x55 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 0x56 | Reserved | 7:0 | Reserved | R/W | 0x10 | Set bits to 0x10 | |
| 0x57 | Reserved | 7:0 | Reserved | R/W | 0x64 | Set bits to 0x64 | |
| 0x58 | Reserved | 7:0 | Reserved | R/W | 0x21 | Set bits to 0x21 | |
| 0x59 | Reserved | 7:1 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 0 | Reserved | Yes | Set bit to 0. | ||||
| 0x5A | Reserved | 7:0 | Reserved | R/W | 0x54 | Yes | Set bits to 0x54 |
| 0x5B | Reserved | 7:0 | Reserved | R/W | 0x54 | Yes | Set bits to 0x54 |
| 0x5C-0x5D | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 0x5E | Override SEL[1:0] and INPUT_EN | 7:3 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 2 | Override SEL1 pin | 1: Block SEL1 pin control; use Reg_5F to configure. 0: Allow SEL1 pin control |
|||||
| 1 | Override SEL0 pin | 1: Block SEL0 pin control; use Reg_5F to configure. 0: Allow SEL0 pin control |
|||||
| 0 | Override INPUT_EN pin | 1: Block INPUT_EN pin control; use Reg_5F to configure. 0: Allow INPUT_EN pin control |
|||||
| 0x5F | Control SEL[1:0] and INPUT_EN | 7:6 | SEL1 Control | R/W | 0x00 | Select for Lane 1. 00: 0 - selects input S_INB1±, output S_OUTB1±. 01: 20 kΩ to GND - selects input S_INB1±, output S_OUTA1± 10: FLOAT - selects input S_INA1±, output S_OUTB1± 11: 1 - selects input S_INA1±, output S_OUTA1±. |
|
| 5:4 | SEL0 Control | Select for Lane 0. 00: 0 - selects input S_INB0±, output S_OUTB0±. 01: 20kΩ to GND - selects input S_INB0±, output S_OUTA0± 10: FLOAT - selects input S_INA0±, output S_OUTB0± 11: 1 - selects input S_INA0±, output S_OUTA0±. |
|||||
| 3:2 | INPUT_EN Control | 1: Block SEL0 pin control; use Reg_5F to configure. 0: Allow SEL0 pin control |
|||||
| 1:0 | Reserved | 1: Block INPUT_EN pin control; use Reg_5F to configure. 0: Allow INPUT_EN pin control |
Table 8. EEPROM Register Map With Default Value
| EEPROM ADDRESS BYTE | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 | ||
|---|---|---|---|---|---|---|---|---|---|---|
| Description | 0x00 | CRC_EN | Address Map Present | EEPROM > 256 Bytes | Reserved | DEVICE COUNT[3] | DEVICE COUNT[2] | DEVICE COUNT[1] | DEVICE COUNT[0] | |
| Default Value | 0x00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x01 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | |
| Default Value | 0x00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x02 | Max EEPROM Burst size[7] | Max EEPROM Burst size[6] | Max EEPROM Burst size[5] | Max EEPROM Burst size[4] | Max EEPROM Burst size[3] | Max EEPROM Burst size[2] | Max EEPROM Burst size[1] | Max EEPROM Burst size[0] | |
| Default Value | 0x00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x03 | PWDN_CH7 | PWDN_CH6 | PWDN_CH5 | PWDN_CH4 | PWDN_CH3 | PWDN_CH2 | PWDN_CH1 | PWDN_CH0 | |
| SMBus Register | 0x01[7] | 0x01[6] | 0x01[5] | 0x01[4] | 0x01[3] | 0x01[2] | 0x01[1] | 0x01[0] | ||
| Default Value | 0x00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x04 | Reserved | Reserved | Reserved | Reserved | Ovrd_RESET | Reserved | Reserved | Reserved | |
| SMBus Register | 0x02[5] | 0x02[4] | 0x02[3] | 0x02[2] | 0x02[0] | 0x04[7] | 0x04[6] | 0x04[5] | ||
| Default Value | 0x00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x05 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | |
| SMBus Register | 0x04[4] | 0x04[3] | 0x04[2] | 0x04[1] | 0x04[0] | 0x06[4] | 0x08[6] | 0x08[5] | ||
| Default Value | 0x04 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | |
| Description | 0x06 | Reserved | Ovrd_RXDET | Ovrd_MODE | Reserved | Reserved | Reserved | Reserved | Reserved | |
| SMBus Register | 0x08[4] | 0x08[3] | 0x08[2] | 0x08[1] | 0x08[0] | 0x0B[6] | 0x0B[5] | 0x0B[4] | ||
| Default Value | 0x07 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | |
| Description | 0x07 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | CH0_RXDET_1 | CH0_RXDET_0 | |
| SMBus Register | 0x0B[3] | 0x0B[2] | 0x0B[1] | 0x0B[0] | 0x0E[5] | 0x0E[4] | 0x0E[3] | 0x0E[2] | ||
| Default Value | 0x00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x08 | CH0_EQ_7 | CH0_EQ_6 | CH0_EQ_5 | CH0_EQ_4 | CH0_EQ_3 | CH0_EQ_2 | CH0_EQ_1 | CH0_EQ_0 | |
| SMBus Register | 0x0F[7] | 0x0F[6] | 0x0F[5] | 0x0F[4] | 0x0F[3] | 0x0F[2] | 0x0F[1] | 0x0F[0] | ||
| Default Value | 0x2F | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | |
| Description | 0x09 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | |
| SMBus Register | 0x10[7] | 0x10[6] | 0x10[5] | 0x10[4] | 0x10[3] | 0x10[2] | 0x10[1] | 0x10[0] | ||
| Default Value | 0xAD | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | |
| Description | 0x0A | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | |
| SMBus Register | 0x11[2] | 0x11[1] | 0x11[0] | 0x12[7] | 0x12[3] | 0x12[2] | 0x12[1] | 0x12[0] | ||
| Default Value | 0x40 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x0B | Reserved | Reserved | CH1_RXDET_1 | CH1_RXDET_0 | CH1_EQ_7 | CH1_EQ_6 | CH1_EQ_5 | CH1_EQ_4 | |
| SMBus Register | 0x15[5] | 0x15[4] | 0x15[3] | 0x15[2] | 0x16[7] | 0x16[6] | 0x16[5] | 0x16[4] | ||
| Default Value | 0x02 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | |
| Description | 0x0C | CH1_EQ_3 | CH1_EQ_2 | CH1_EQ_1 | CH1_EQ_0 | CH1_SCP | CH1_Sel_MODE | Reserved | Reserved | |
| SMBus Register | 0x16[3] | 0x16[2] | 0x16[1] | 0x16[0] | 0x17[7] | 0x17[6] | 0x17[5] | 0x17[4] | ||
| Default Value | 0xFA | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | |
| Description | 0x0D | Reserved | CH1_VOD_2 | CH1_VOD_1 | CH1_VOD_0 | CH1_DEM_2 | CH1_DEM_1 | CH1_DEM_0 | Reserved | |
| SMBus Register | 0x17[3] | 0x17[2] | 0x17[1] | 0x17[0] | 0x18[2] | 0x18[1] | 0x18[0] | 0x19[7] | ||
| Default Value | 0xD4 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | |
| Description | 0x0E | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | CH2_RXDET_1 | CH2_RXDET_0 | |
| SMBus Register | 0x19[3] | 0x19[2] | 0x19[1] | 0x19[0] | 0x1C[5] | 0x1C[4] | 0x1C[3] | 0x1C[2] | ||
| Default Value | 0x00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x0F | CH2_EQ_7 | CH2_EQ_6 | CH2_EQ_5 | CH2_EQ_4 | CH2_EQ_3 | CH2_EQ_2 | CH2_EQ_1 | CH2_EQ_0 | |
| SMBus Register | 0x1D[7] | 0x1D[6] | 0x1D[5] | 0x1D[4] | 0x1D[3] | 0x1D[2] | 0x1D[1] | 0x1D[0] | ||
| Default Value | 0x2F | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | |
| Description | 0x10 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | |
| SMBus Register | 0x1E[7] | 0x1E[6] | 0x1E[5] | 0x1E[4] | 0x1E[3] | 0x1E[2] | 0x1E[1] | 0x1E[0] | ||
| Default Value | 0xAD | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | |
| Description | 0x11 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | |
| SMBus Register | 0x1F[2] | 0x1F[1] | 0x1F[0] | 0x20[7] | 0x20[3] | 0x20[2] | 0x20[1] | 0x20[0] | ||
| Default Value | 0x40 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x12 | Reserved | Reserved | CH3_RXDET_1 | CH3_RXDET_0 | CH3_EQ_7 | CH3_EQ_6 | CH3_EQ_5 | CH3_EQ_4 | |
| SMBus Register | 0x23[5] | 0x23[4] | 0x23[3] | 0x23[2] | 0x24[7] | 0x24[6] | 0x24[5] | 0x24[4] | ||
| Default Value | 0x02 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | |
| Description | 0x13 | CH3_EQ_3 | CH3_EQ_2 | CH3_EQ_1 | CH3_EQ_0 | CH3_SCP | CH3_Sel_MODE | Reserved | Reserved | |
| SMBus Register | 0x24[3] | 0x24[2] | 0x24[1] | 0x24[0] | 0x25[7] | 0x25[6] | 0x25[5] | 0x25[4] | ||
| Default Value | 0xFA | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | |
| Description | 0x14 | Reserved | CH3_VOD_2 | CH3_VOD_1 | CH3_VOD_0 | CH3_DEM_2 | CH3_DEM_1 | CH3_DEM_0 | Reserved | |
| SMBus Register | 0x25[3] | 0x25[2] | 0x25[1] | 0x25[0] | 0x26[2] | 0x26[1] | 0x26[0] | 0x27[7] | ||
| Default Value | 0xD4 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | |
| Description | 0x15 | Reserved | Reserved | Reserved | Reserved | Reserved | hi_idle_SD CH0-3 | hi_idle_SD CH4-7 | fast_SD CH0-3 | |
| SMBus Register | 0x27[3] | 0x27[2] | 0x27[1] | 0x27[0] | 0x28[6] | 0x28[5] | 0x28[4] | 0x28[3] | ||
| Default Value | 0x01 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
| Description | 0x16 | fast_SD CH4-7 | lo_gain_SD CH0-3 | lo_gain_SD CH4-7 | Reserved | Reserved | CH4_RXDET_1 | CH4_RXDET_0 | CH4_EQ_7 | |
| SMBus Register | 0x28[2] | 0x28[1] | 0x28[0] | 0x2B[5] | 0x2B[4] | 0x2B[3] | 0x2B[2] | 0x2C[7] | ||
| Default Value | 0x80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x17 | CH4_EQ_6 | CH4_EQ_5 | CH4_EQ_4 | CH4_EQ_3 | CH4_EQ_2 | CH4_EQ_1 | CH4_EQ_0 | CH4_SCP | |
| SMBus Register | 0x2C[6] | 0x2C[5] | 0x2C[4] | 0x2C[3] | 0x2C[2] | 0x2C[1] | 0x2C[0] | 0x2D[7] | ||
| Default Value | 0x5F | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | |
| Description | 0x18 | CH4_Sel_MODE | Reserved | Reserved | Reserved | CH4_VOD_2 | CH4_VOD_1 | CH4_VOD_0 | CH4_DEM_2 | |
| SMBus Register | 0x2D[6] | 0x2D[5] | 0x2D[4] | 0x2D[3] | 0x2D[2] | 0x2D[1] | 0x2D[0] | 0x2E[2] | ||
| Default Value | 0x5A | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | |
| Description | 0x19 | CH4_DEM_1 | CH4_DEM_0 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | |
| SMBus Register | 0x2E[1] | 0x2E[0] | 0x2F[7] | 0x2F[3] | 0x2F[2] | 0x2F[1] | 0x2F[0] | 0x32[5] | ||
| Default Value | 0x80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x1A | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | |
| SMBus Register | 0x32[4] | 0x32[3] | 0x32[2] | 0x33[7] | 0x33[6] | 0x33[5] | 0x33[4] | 0x33[3] | ||
| Default Value | 0x05 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | |
| Description | 0x1B | Reserved | Reserved | Reserved | CH5_SCP | CH5_Sel_MODE | Reserved | Reserved | Reserved | |
| SMBus Register | 0x33[2] | 0x33[1] | 0x33[0] | 0x34[7] | 0x34[6] | 0x34[5] | 0x34[4] | 0x34[3] | ||
| Default Value | 0xF5 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | |
| Description | 0x1C | CH5_VOD_2 | CH5_VOD_1 | CH5_VOD_0 | CH5_DEM_2 | CH5_DEM_1 | CH5_DEM_0 | Reserved | Reserved | |
| SMBus Register | 0x34[2] | 0x34[1] | 0x34[0] | 0x35[2] | 0x35[1] | 0x35[0] | 0x36[7] | 0x36[3] | ||
| Default Value | 0xA8 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | |
| Description | 0x1D | Reserved | Reserved | Reserved | Reserved | Reserved | CH6_RXDET_1 | CH6_RXDET_0 | CH6_EQ_7 | |
| SMBus Register | 0x36[2] | 0x36[1] | 0x36[0] | 0x39[5] | 0x39[4] | 0x39[3] | 0x39[2] | 0x3A[7] | ||
| Default Value | 0x00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x1E | CH6_EQ_6 | CH6_EQ_5 | CH6_EQ_4 | CH6_EQ_3 | CH6_EQ_2 | CH6_EQ_1 | CH6_EQ_0 | CH6_SCP | |
| SMBus Register | 0x3A[6] | 0x3A[5] | 0x3A[4] | 0x3A[3] | 0x3A[2] | 0x3A[1] | 0x3A[0] | 0x3B[7] | ||
| Default Value | 0x5F | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | |
| Description | 0x1F | CH6_Sel_MODE | Reserved | Reserved | Reserved | CH6_VOD_2 | CH6_VOD_1 | CH6_VOD_0 | CH6_DEM_2 | |
| SMBus Register | 0x3B[6] | 0x3B[5] | 0x3B[4] | 0x3B[3] | 0x3B[2] | 0x3B[1] | 0x3B[0] | 0x3C[2] | ||
| Default Value | 0x5A | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | |
| Description | 0x20 | CH6_DEM_1 | CH6_DEM_0 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | |
| SMBus Register | 0x3C[1] | 0x3C[0] | 0x3D[7] | 0x3D[3] | 0x3D[2] | 0x3D[1] | 0x3D[0] | 0x40[5] | ||
| Default Value | 0x80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x21 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | |
| SMBus Register | 0x40[4] | 0x40[3] | 0x40[2] | 0x41[7] | 0x41[6] | 0x41[5] | 0x41[4] | 0x41[3] | ||
| Default Value | 0x05 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | |
| Description | 0x22 | Reserved | Reserved | Reserved | CH7_SCP | CH7_Sel_MODE | Reserved | Reserved | Reserved | |
| SMBus Register | 0x41[2] | 0x41[1] | 0x41[0] | 0x42[7] | 0x42[6] | 0x42[5] | 0x42[4] | 0x42[3] | ||
| Default Value | 0xF5 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | |
| Description | 0x23 | CH7_VOD_2 | CH7_VOD_1 | CH7_VOD_0 | CH7_DEM_2 | CH7_DEM_1 | CH7_DEM_0 | Reserved | Reserved | |
| SMBus Register | 0x42[2] | 0x42[1] | 0x42[0] | 0x43[2] | 0x43[1] | 0x43[0] | 0x44[7] | 0x44[3] | ||
| Default Value | 0xA8 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | |
| Description | 0x24 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | |
| SMBus Register | 0x44[2] | 0x44[1] | 0x44[0] | 0x47[3] | 0x47[2] | 0x47[1] | 0x47[0] | 0x48[7] | ||
| Default Value | 0x00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x25 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | |
| SMBus Register | 0x48[6] | 0x4C[7] | 0x4C[6] | 0x4C[5] | 0x4C[4] | 0x4C[3] | 0x4C[0] | 0x59[0] | ||
| Default Value | 0x00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x26 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | |
| SMBus Register | 0x5A[7] | 0x5A[6] | 0x5A[5] | 0x5A[4] | 0x5A[3] | 0x5A[2] | 0x5A[1] | 0x5A[0] | ||
| Default Value | 0x54 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | |
| Description | 0x27 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | |
| SMBus Register | 0x5B[7] | 0x5B[6] | 0x5B[5] | 0x5B[4] | 0x5B[3] | 0x5B[2] | 0x5B[1] | 0x5B[0] | ||
| Default Value | 0x54 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | |