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ZHCS749B January 2012 – January 2015 DS100DF410

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RHS|48
- MPQF159B

散熱焊盤機械數據 (封裝 | 引腳)

RHS|48
- QFND509A

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings ⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
Supply Voltage (V_DD)	–0.5	2.75	V
2.5 I/O Voltage (LVCMOS and Analog)	–0.5	2.75	V
3.3 LVCMOS I/O Voltage (SDA, SDC, INT)	–0.5	4.0	V
Signal Input Voltage (RXPn, RXNn)	–0.5	2.75	V
Signal Output Voltage (TXPn, TXNn)	–0.5	2.75	V
Junction Temperature		150	°C
Storage Temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	ESD Rating	Human Body Model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±6000	V
		Machine Model (MM), STD - JESD22-A115-A⁽³⁾	±250
		Charged Device Model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1250

(1) JEDEC document JEP155 states that 6000-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 1250-V CDM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V MM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	NOM	MAX	UNIT
Supply Voltage (V_DD to GND)	2.375	2.5	2.625	V
Ambient Temperature	-40	25	+85	°C

6.4 Thermal Information⁽²⁾

THERMAL METRIC⁽¹⁾		DS100DF410	UNIT
		WQFN
		48 PINS
R_θJA	Junction-to-ambient thermal resistance	26.1	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) No airflow, 4-layer JEDEC, 9 thermal vias

6.5 Electrical Characteristics

Over recommended operating supply and temperature ranges with default register settings unless otherwise specified. ⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER
PD	Power supply consumption	Average Power Consumption⁽²⁾		720		mW
PD	Power supply consumption	Max Transient Power Supply Current ⁽³⁾		500	610	mA
NT_PS	Supply noise tolerance ⁽⁴⁾	50 Hz to 100 Hz		100		mV_P-P
		100 Hz to 10 MHz		40		mV_P-P
		10 MHz to 5.0 GHz		10		mV_P-P
2.5V LVCMOS DC SPECIFICATIONS
V_IH	High level input voltage		1.75		V_DD	V
V_IH	High level (ADDR[3:0] pins)		2.28		VDD	V
V_IL	Low level input voltage		GND		0.7	V
V_IL	Low level input voltage (ADDR[3:0] pins)		GND		0.335	V
V_OH	High level output voltage	I_OH = -3mA	2.0			V
V_OL	Low level output voltage	I_OL = 3mA			0.4	V
I_IN	Input leakage current	V_IN = V_DD			10	μA
I_IN	Input leakage current	V_IN = GND	–10			μA
I_IH	Input high current (EN_SMB pin)	V_IN = V_DD		55		μA
I_IL	Input low current (EN_SMB pin)	V_IN = GND		–110		μA
3.3 V LVCMOS DC SPECIFICATIONS (SDA, SDC, INT)
V_IH	High level input voltage	V_DD = 2.5 V	1.75		3.6	V
V_IL	Low level input voltage	V_DD = 2.5 V	GND		0.7	V
V_OL	Low level output voltage	I_PULLUP = 3mA			0.4	V
I_IH	Input high current	V_IN = 3.6 V, V_DD = 2.5 V	20		40	μA
I_IL	Input low current	V_IN = GND, V_DD = 2.5 V	–10		10	μA
f_SDC	SMBus clock rate	Slave Mode	10		400	kHz
f_SDC	SMBus clock rate	Master Mode⁽⁵⁾		400		kHz
DATA BIT RATES
R_B	Bit rate range	10.3125 Gbps Ethernet	10.1		10.6	Gbps
R_B	Bit rate range	1.25 Gbps Ethernet	1.2		1.3	Gbps
SIGNAL DETECT
SDH	Signal detect ON threshold level	Default differential input signal level to assert signal detect, 10.3125 Gbps, PRBS-31		70		mV_p-p
SDL	Signal detect OFF threshold level	Default differential input signal level to de-assert signal detect, 10.3125 Gbps, PRBS-31		10		mV_p-p
RECEIVER INPUTS (RXPn, RXNn)
V_{TX2, min}	Minimum source transmit launch signal level (IN, diff)	See ⁽⁵⁾		600		mV_P-P
V_{TX2, max}		See ⁽⁵⁾		1000		mV_P-P
V_{TX1, max}		See ⁽⁶⁾		1200		mV_P-P
V_{TX0, max}		See ⁽⁷⁾		1600		mV_P-P
L_RI	Maximum differential input return loss - \|SDD11\|	100 MHz – 6 GHz⁽⁸⁾		-15		dB
Z_D	Differential input impedance	100 MHz – 6 GHz		100		Ω
Z_S	Single-ended input impedance	100 MHz – 6 GHz		50		Ω
DRIVER OUTPUTS (TXPn, TXNn)
V_OD0	Differential output voltage	Differential measurement with OUT+ and OUT- terminated by 50Ω to GND, AC-Coupled, SMBus register VOD control (Register 0x2d bits 2:0) set to 0, minimum VOD De-emphasis control set to minimum (0 dB)	400		675	mV_P-P
V_OD7	Differential output voltage	Differential measurement with OUT+ and OUT- terminated by 50Ω to GND, AC-Coupled SMBus register VOD control (Register 0x2d bits 2:0) set to 7, maximum VOD De-emphasis control set to minimum (0 dB)	1000			mV_P-P
V_{OD_DE}	De-emphasis level ⁽¹⁰⁾	Differential measurement with OUT+ and OUT- terminated by 50Ω to GND, AC-Coupled Set by SMBus register control to maximum de-emphasis setting Relative to the nominal 0 dB de-emphasis level set at the minimum de-emphasis setting		-12		dB
t_R, t_F	Transition time (rise and fall times)⁽¹⁰⁾⁽¹¹⁾	Transition time control = Full Slew Rate		39		ps
t_R, t_F	Transition time (rise and fall times)⁽¹⁰⁾⁽¹¹⁾	Transition time control = Limited Slew Rate		50		ps
L_RO	Maximum differential output return loss - \|SDD22\|	100 MHz – 6 GHz ⁽⁸⁾		–15		dB
t_DP	Propagation delay	Retimed data⁽⁹⁾		300		ps
T_DE	De-emphasis pulse duration⁽¹²⁾	Measured at V_OD = 1000 mV_P-P, de-emphasis setting = -12 dB		75		ps
TJ	Output total jitter	Measured at BER = 10^-12⁽¹³⁾		10		ps
T_SKEW	Intra pair skew	Difference in 50% crossing between TXPn and TXNn for any output		3		ps
T_SKEW	Channel-to-channel skew			7		ps
CLOCK AND DATA RECOVERY
BW_PLL	PLL Bandwidth, -3 dB	Measured at 10.3125 Gbps		5		MHz
J_TOL	Input sinusoidal jitter tolerance 10 kHz to 250 MHz sinusoidal jitter frequency	Measured at BER = 10^-15		0.6		UI
J_TRANS	Jitter transfer sinusoidal jitter at 10 MHz jitter frequency	Measured at BER = 10^-15		-6		dB
T_LOCK	CDR Lock Time	Measured at 10.3125 Gbps		15		ms
RECOMMENDED REFERENCE CLOCK SPECS
REF_f	Input reference clock frequency		24.9975	25	25.0025	MHz
REFCLK_IN_PW	Minimum REFCLK_IN Pulse Width	At REFCLK_IN pin		4		ns
REFCLK_ OUT_DCD	REFCLK_OUT duty cycle distortion	C_L = 5 pF		0.55		ns
REF_VIH	Reference clock input min high threshold			1.75		V
REF_VIL	Reference clock input max low threshold			0.7		V

(1) Typical values represent most likely parametric norms at V_DD = 2.5V, T_A = 25°C, and at the Recommended Operation Conditions at the time of product characterization.

(2) V_DD= 2.5V, T_A = 25°C. All four channels active and locked. DFE powered-up and enabled.

(3) Maximum power supply current during lock acquisition. All four channels active, all four channels unlocked, all registers at default settings.

(4) Allowed supply noise (mV_P-P sine wave) under typical conditions.

(5) EEPROM device used for Master mode programming must support fSDC greater than 400kHz.

(6) Differential signal amplitude at the transmitter output providing < 1x10^-12 bit error rate. Measured at 10.3125 Gbps with a PRBS-31 data pattern. Input transmission channel is 40-inch long FR-4 stripline, 4-mil trace width.

(7) Differential signal amplitude at the transmitter output providing < 1x10^-12 bit error rate. Measured at 10.3125 Gbps with a PRBS-31 data pattern. No input transmission channel.

(8) Measured with 10 MHz clock pattern output.

(9) Typical at 10.3125 Gbps bit rate.

(10) Measured with clock-like {11111 00000} pattern.

(11) Slew rate is controlled by SMBus register settings.

(12) De-emphasis pulse width varies with V_OD and de-emphasis settings.

(13) Typical with no output de-emphasis, minimum output transmission channel.

6.6 Typical Characteristics

Figure 1. Typical VOD vs VDD

Figure 2. Typical VOD vs Temperature