ZHCS749B January 2012 – January 2015 DS100DF410
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Device Data Path Operation
- 7.3.2 Signal Detect
- 7.3.3 CTLE
- 7.3.4 DFE
- 7.3.5 Clock and Data Recovery
- 7.3.6 Output Driver
- 7.3.7 CTLE Boost Setting
- 7.3.8 DFE Tap Weight and Polarity Setting
- 7.3.9 Driver Output Voltage
- 7.3.10 Driver Output De-Emphasis
- 7.3.11 Driver Output Rise/Fall Time
- 7.3.12 Ref_mode 0 Mode (Reference Clock Not Required)
- 7.3.13 Ref_mode 3 Mode (Reference Clock Required)
- 7.3.14 False Lock Detector Setting
- 7.3.15 Reference Clock In
- 7.3.16 Reference Clock Out
- 7.3.17 Daisy Chain of REFCLK_OUT to REFCLK_IN
- 7.3.18 INT
- 7.3.19 LOCK_3, LOCK_2, LOCK_1, and LOCK_0
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1 SMBus Strap Observation
- 7.5.2 Device Revision and Device ID
- 7.5.3 Control/Shared Register Reset
- 7.5.4 Interrupt Channel Flag Bits
- 7.5.5 SMBus Master Mode Control Bits
- 7.5.6 Resetting Individual Channels of the Retimer
- 7.5.7 Interrupt Status
- 7.5.8 Overriding the CTLE Boost Setting
- 7.5.9 Overriding the VCO CAP DAC Values
- 7.5.10 Overriding the Output Multiplexer
- 7.5.11 Overriding the VCO Divider Selection
- 7.5.12 Using the PRBS Generator
- 7.5.13 Using the Internal Eye Opening Monitor
- 7.5.14 Overriding the DFE Tap Weights and Polarities
- 7.5.15 Enabling Slow Rise/Fall Time on the Output Driver
- 7.5.16 Inverting the Output Polarity
- 7.5.17 Overriding the Figure of Merit for Adaptation
- 7.5.18 Setting the Rate and Subrate for Lock Acquisition
- 7.5.19 Setting the Adaptation/Lock Mode
- 7.5.20 Initiating Adaptation
- 7.5.21 Setting the Reference Enable Mode
- 7.5.22 Overriding the CTLE Settings Used for CTLE Adaptation
- 7.5.23 Setting the Output Differential Voltage
- 7.5.24 Setting the Output De-emphasis Setting
- 7.6 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械封裝和可訂購信息
5 Pin Configuration and Functions
RHS Package
48 Pins
Top View
Pin Functions
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NUMBER | ||
| HIGH-SPEED DIFFERENTIAL I/O | |||
| RXP0 RXN0 |
1 2 |
I, CML | Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal differential input impedance = 100Ω. Must be AC coupled. |
| RXP1 RXN1 |
4 5 |
I, CML | Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal differential input impedance = 100Ω. Must be AC coupled. |
| RXP2 RXN2 |
8 9 |
I, CML | Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal differential input impedance = 100Ω. Must be AC coupled. |
| RXP3 RXN3 |
11 12 |
I, CML | Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal differential input impedance = 100Ω. Must be AC coupled. |
| TXP0 TXN0 |
36 35 |
O, CML | Inverting and non-inverting CML-compatible differential outputs from the driver. Nominal differential output impedance = 100Ω. Must be AC coupled. |
| TXP1 TXN1 |
33 32 |
O, CML | Inverting and non-inverting CML-compatible differential outputs from the driver. Nominal differential output impedance = 100Ω. Must be AC coupled. |
| TXP2 TXN2 |
29 28 |
O, CML | Inverting and non-inverting CML-compatible differential outputs from the driver. Nominal differential output impedance = 100Ω. Must be AC coupled. |
| TXP3 TXN3 |
26 25 |
O, CML | Inverting and non-inverting CML-compatible differential outputs from the driver. Nominal differential output impedance = 100Ω. Must be AC coupled. |
| LOOP FILTER CONNECTION PINS | |||
| LPF_CP_0 LPF_REF_0 |
47 48 |
I/O, analog | Loop filter connection Place a 22 nF ± 10% Capacitor between LPF_CP_0 and LPF_REF_0 |
| LPF_CP_1 LPF_REF_1 |
38 37 |
I/O, analog | Loop filter connection Place a 22 nF ± 10% Capacitor between LPF_CP_1 and LPF_REF_1 |
| LPF_CP_2 LPF_REF_2 |
23 24 |
I/O, analog | Loop filter connection Place a 22 nF ± 10% Capacitor between LPF_CP_2 and LPF_REF_2 |
| LPF_CP_3 LPF_REF_3 |
14 13 |
I/O, analog | Loop filter connection Place a 22 nF ± 10% Capacitor between LPF_CP_3 and LPF_REF_3 |
| REFERENCE CLOCK I/O | |||
| REFCLK_IN | 19 | I, 2.5V analog | Input is 2.5 V, 25 MHz ± 100 ppm reference clock from external oscillator No stringent phase noise requirement |
| REFCLK_OUT | 42 | O, 2.5V analog | Output is 2.5 V, buffered replica of reference clock input for connecting multiple DS100DF410s on a board |
| LOCK INDICATOR PINS | |||
| LOCK_0 LOCK_1 LOCK_2 LOCK_3 |
45 40 21 16 |
O, 2.5V LVCMOS | Output is 2.5 V, the pin is high when CDR lock is attained on the corresponding channel Note that these pins are shared with SMBus address strap input functions read at startup. |
| SMBus MASTER MODE PINS | |||
| ALL_DONE | 41 | O, 2.5V LVCMOS | Output is 2.5 V, the pin goes low to indicate that the SMBus master EEPROM read has been completed. |
| READ_EN | 44 | I, 2.5V LVCMOS | Input is 2.5 V, a transition from high to low starts the load from the external EEPROM. The READ_EN pin must be tied low when in SMBus slave mode |
| INTERRUPT OUTPUT | |||
| INT | 43 | O, 3.3V LVCMOS, Open Drain | Used to signal horizontal or vertical eye opening out of tolerance, loss of signal detect, or CDR unlock External 2KΩ to 5KΩ pull-up resistor is required. Pin is 3.3 V LVCMOS tolerant. |
| SERIAL MANAGEMENT BUS (SMBus) INTERFACE | |||
| EN_SMB | 20 | I, 2.5V analog | Input is 2.5 V, selects SMBus master mode or SMBus slave mode EN_SMB = High for slave mode EN_SMB = Float for master mode Tie READ_EN pin low for SMBus slave mode. See Table 1 |
| SDA | 18 | I/O, 3.3V LVCMOS, Open Drain | Data Input / Open Drain Output External 2KΩ to 5KΩ pull-up resistor is required. Pin is 3.3 V LVCMOS tolerant. |
| SDC | 17 | I/O, 3.3V LVCMOS, Open Drain | Clock Input / Open Drain Clock Output External 2KΩ to 5KΩ pull-up resistor is required. Pin is 3.3 V LVCMOS tolerant. |
| ADDR_0 ADDR_1 ADDR_2 ADDR_3 |
45 40 21 16 |
I, 2.5V LVCMOS | Input is 2.5 V, the ADDR_[3:0] pins set the SMBus address for the retimer. These pins are strap inputs. Their state is read on power-up to set the SMBus address in SMBus control mode. High = 1KΩ to VDD, Low = 1KΩ to GND Note that these pins are shared with the lock indicator functions. See Table 2 |
| POWER | |||
| VDD | 3, 6, 7, 10, 15, 46 |
Power | VDD = 2.5 V ± 5% |
| GND | 22, 27, 30, 31, 34, 39 |
Power | Ground reference. |
| DAP | PAD | Power | Ground reference. The exposed pad at the center of the package must be connected to ground plane of the board with at least 4 vias to lower the ground impedance and improve the thermal performance of the package. |
(1) Notes: I = Input, O = Output and 2.5V LVCMOS pins are 2.5 V levels only.
Only SMBus pins SDA and SDC and INT pin are 3.3 V tolerant. These three pins are open-drain and require external pull-up resistors.
Only SMBus pins SDA and SDC and INT pin are 3.3 V tolerant. These three pins are open-drain and require external pull-up resistors.