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SNLS338F January 2011 – November 2014 DS100BR111

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RTW|24
- MPQF167C

散熱焊盤機械數據 (封裝 | 引腳)

RTW|24
- QFND450A

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾

	MIN	MAX	UNIT
Supply Voltage (VDD)	-0.5	+2.75	V
Supply Voltage (VIN)	-0.5	+4.0	V
LVCMOS Input/Output Voltage	-0.5	+4.0	V
CML Input Voltage	-0.5	(VDD+0.5)	V
CML Input Current	-30	+30	mA
Junction Temperature		125	°C

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied.

(2) For soldering specifications, see SNOA549.

7.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage Temperature Range		-40	+125	°C
V_(ESD)	Electrostatic Discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	-5	5	kV
		Machine model (MM), STD - JESD22-A115-A		100	V
		Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾		1250	V

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions⁽¹⁾

	MIN	TYP	MAX	UNIT
Supply Voltage (2.5 V mode)	2.375	2.5	2.625	V
Supply Voltage (3.3 V mode)	3.0	3.3	3.6	V
Ambient Temperature	-40	25	+85	°C
SMBus (SDA, SCL)			3.6	V

(1) The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute Maximum Numbers are ensured for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating Voltages only.

7.4 Electrical Characteristics

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLY CURRENT
IDD	Supply Current	TX_DIS = Low, EQ = ON VOD_SEL = Float (1000 mVpp)		50	63	mA
		Auto Low Power Mode TX_DIS = Low, MODE = 20 kΩ VID CHA and CHB = 0.0 V VOD_SEL = Float (1000 mVpp)		12	15
		TX_DIS = High		25	35
LVCMOS DC SPECIFICATIONS
V_IH25	High Level Input Voltage, 2-Level LVCMOS	2.5 V Supply Mode	2.0		VDD	V
V_IH33	High Level Input Voltage, 2-Level LVCMOS	3.3 V Supply Mode	2.0		VIN	V
V_IL	Low Level Input Voltage, 2-Level LVCMOS		GND		0.7	V
V_OH	High Level Output Voltage	I_OH = -4.0 mA ⁽³⁾	2.0			V
V_OL	Low Level Output Voltage	I_OL = 4.0 mA			0.4	V
I_IN	Input Leakage Current	Vinput = 0 V or VDD VDD_SEL = Float	-15		+15	µA
I_IN	Input Leakage Current	Vinput = 0 V or VIN VDD_SEL = Low	-15		+15	µA
I_IN-P	Input Leakage Current 4-Level Input ⁽¹⁾	Vinput = 0 V or VDD - 0.05 V VDD_SEL = Float Vinput = 0 V or VIN - 0.05 V VDD_SEL = Low	-160		+80	µA
CML RECEIVER INPUTS
V_TX	Source Transmit Launch Differential Signal Level	Default power-up conditions ENSMB = 0 or 1	190	800	1600	mVp-p
RL_RX-IN	RX return loss	SDD11 @ 4.1 GHz		-12		dB
		SDD11 @ 11.1 GHz		-8
		SCD11 @ 11.1 GHz		-10
HIGH SPEED TRANSMITTER OUTPUTS
V_OD1	Output Voltage Differential Swing	OUT+ and OUT- AC coupled and terminated by 50 Ω to GND VOD_SEL = Low (700 mVpp setting) DE = Low	500	650	800	mVp-p
V_OD2	Output Voltage Differential Swing	OUT+ and OUT- AC coupled and terminated by 50 Ω to GND VOD_SEL = Float (1000 mVpp setting) DE = Low	800	1000	1100
V_OD3	Output Voltage Differential Swing	OUT+ and OUT- AC coupled and terminated by 50 Ω to GND VOD_SEL = 20 kΩ to GND (1200 mVpp) DE = Low	950	1150	1350
V_{OD_DE1}	De-Emphasis Levels	OUT+ and OUT- AC coupled and terminated by 50 Ω to GND VOD_SEL = Float (1000 mVpp) DE = Float		-3		dB
V_{OD_DE2}	De-Emphasis Levels	OUT+ and OUT- AC coupled and terminated by 50 Ω to GND VOD_SEL = Float (1000 mVpp) DE = 20 kΩ to GND		-6		dB
V_{OD_DE3}	De-Emphasis Levels	OUT+ and OUT- AC coupled and terminated by 50 Ω to GND VOD_SEL = Float (1000 mVpp) DE = High		-9		dB
V_CM-AC	Output Common-Mode Voltage	AC Common Mode Voltage DE = 0 dB, VOD ≤ 1000 mVpp		4.5		mV (rms)
V_CM-DC	Output DC Common-Mode Voltage	DC Common Mode Voltage	0	1.1	1.9	V
V_IDLE	TX IDLE Output Voltage	VID = 0 mVp-p			30	mV
RL_TX-DIFF	TX return loss	SDD22 @ 4.1 GHz		-13		dB
		SDD22 @ 11.1 GHz		-9
		SCC22 @ 2.5 GHz		-22
		SCC22 @ 11.1 GHz		-10
Delta_Z_M	Transmitter Termination Mismatch	DC, I_FORCE = ± 100 µA ⁽⁴⁾		2.5%
T_R/F	Transmitter Rise and Fall Time	Measurement points at 20% - 80% ⁽⁷⁾		38		ps
T_PD	Propagation Delay	Measured at 50% crossing EQ = 0x00		230		ps
T_CCSK	Channel to Channel Skew	T = 25°C, VDD = 2.5 V		7		ps
T_PPSK	Part to Part Skew	T = 25°C, VDD = 2.5 V		20		ps
T_{TX-IDLE-SET-TO-IDLE}	Max time to transition to idle after differential signal	VIN = 1 Vpp, 10 Gbps EQ = 0x00, DE = 0 dB		6.5		ns
T_{TX-IDLE-TO-DIFF-DATA}	Max time to transition to valid differential signal after idle	VIN = 1 Vpp, 10 Gbps EQ = 0x00, DE = 0 dB		3.2		ns
T_{ENV_DISTORT}	Active OOB timing distortion, input active time vs. output active time			3.3		ns
OUTPUT JITTER SPECIFICATIONS⁽²⁾
R_J	Random Jitter	No Media Source Amplitude = 700 mVpp, PRBS15 pattern, 10.3125 Gbps VOD = Default, EQ = minimum, DE = 0 dB		0.3		ps (rms)
D_J1	Deterministic Jitter			0.09		UI
EQUALIZATION
D_JE1	Residual Deterministic Jitter	10.3125 Gbps 8 meter 30AWG Cable on Input Source = 700 mVpp, PRBS15 pattern EQ = 0x0F		0.27		UI
D_JE2	Residual Deterministic Jitter	10.3125 Gbps 30" 4-mil FR4 on Inputs Source = 700 mVpp, PRBS15 pattern EQ = 0x16		0.17		UI
DE-EMPHASIS
D_JD1	Residual Deterministic Jitter	10.3125 Gbps 10” 4 mil stripline FR4 on Outputs Source = 700 mVpp, PRBS15 pattern EQ = Min, VOD = 1200 mVpp, DE = -3.5 dB		0.13		UI

(1) Input is held to a maximum of 50 mV below VDD or VIN to simulate the use of a 1 kΩ resistor on the input.

(2) Typical jitter reported is determined by jitter decomposition software on the DSA8200 Oscilloscope.

(3) VOH only applies to the DONE pin; LOS, SCL, and SDA are open-drain outputs that have no internal pull-up capability. DONE is a full LVCMOS output with pull-up and pull-down capability.

(4) Force ±100 µA on output, measure ΔV on the Output and calculate impedance. Mismatch is the percentage difference of OUTn+ and OUTn- impedance driving the same logic state.

(5) Parameter not tested in production.

7.5 Electrical Characteristics — Serial Management Bus Interface

Over recommended operating supply and temperature ranges unless other specified.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SERIAL BUS INTERFACE DC SPECIFICATIONS⁽¹⁾
V_IL	Data, Clock Input Low Voltage				0.8	V
V_IH	Data, Clock Input High Voltage		2.1		3.6	V
I_PULLUP	Current Through Pull-Up Resistor or Current Source	High Power Specification	4			mA
V_DD	Nominal Bus Voltage		2.375		3.6	V
I_LEAK-Bus	Input Leakage Per Bus Segment	See ⁽²⁾	-200		+200	µA
C_I	Capacitance for SDA and SCL	See ⁽²⁾⁽³⁾⁽⁶⁾			10	pF
R_TERM	External Termination Resistance pull to V_DD = 2.5V ± 5% OR 3.3V ± 10%	Pullup V_DD = 3.3 V, See ⁽²⁾⁽³⁾⁽⁴⁾		2000		Ω
R_TERM		Pullup V_DD = 2.5 V, See ⁽²⁾⁽³⁾⁽⁴⁾		1000		Ω
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB	Bus Operating Frequency	ENSMB = VDD (Slave Mode)			400	kHz
FSMB	Bus Operating Frequency	ENSMB = Float (Master Mode) ⁽¹⁾	280	400	520	kHz
T_BUF	Bus Free Time Between Stop and Start Condition		1.3			µs
T_HD:STA	Hold time after (Repeated) Start Condition. After this period, the first clock is generated.	At I_PULLUP, Max	0.6			µs
T_SU:STA	Repeated Start Condition Setup Time		0.6			µs
T_SU:STO	Stop Condition Setup Time		0.6			µs
T_HD:DAT	Data Hold Time		0			ns
T_SU:DAT	Data Setup Time		100			ns
T_LOW	Clock Low Period		1.3			µs
T_HIGH	Clock High Period	See ⁽⁵⁾	0.6		50	µs
t_F	Clock/Data Fall Time	See ⁽⁵⁾			300	ns
t_R	Clock/Data Rise Time	See ⁽⁵⁾			300	ns
t_POR	Time in which a device must be operational after power-on reset	See ⁽⁶⁾⁽⁵⁾			500	ms

(1) EEPROM interface requires 1 MHz capable EEPROM device.

(2) Recommended value.

(3) Recommended maximum capacitance load per bus segment is 400 pF.

(4) Maximum termination voltage should be identical to the device supply voltage.

(5) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common AC specifications for details.

(6) Ensured by design and characterization. Parameter not tested in production.

(7) Default VOD used for testing. DE = -1.5 dB level used to compensate for fixture attenuation.

7.6 Timing Requirements — LOS and ENABLE / DISABLE Timing

	PARAMETER	TEST CONDITIONS	TYP	UNIT
T_{LOS_OFF}	Input IDLE to Active RX_LOS response time	See ⁽⁵⁾	0.035	µs
T_{LOS_ON}	Input Active to IDLE RX_LOS response time	See ⁽⁵⁾	0.4	µs
T_OFF	TX Disable assert Time TX_DIS = High to Output OFF	See ⁽⁵⁾	0.005	µs
T_ON	TX Disable negateTime TX_DIS = Low to Output ON	See ⁽⁵⁾	0.150	µs
T_{LP_EXIT}	Auto Low Power Exit ALP to Normal Operation	See ⁽⁵⁾	150	ns
T_{LP_ENTER}	Auto Low Power Enter Normal Operation to Auto Low Power	See ⁽⁵⁾	100	µs