ZHCSG92A June 2014 – March 2017 DRV8846
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGE|24
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGE|24
訂購(gòu)信息
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature referenced with respect to GND (unless otherwise noted)(1)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Power supply voltage (VM) | –0.3 | 20 | V | |
| Power supply voltage ramp rate (VM) | 0 | 2 | V/µs | |
| Internal regulator voltage (VINT) | –0.3 | 3.6 | V | |
| Analog input pin voltage (VREF) | –0.3 | 3.6 | V | |
| Control pin voltage (nENABLE, STEP, DIR, I0, I1, M0, M1, DEC0, DEC1, TOFF_SEL, nSLEEP, nFAULT, ADEC) | –0.3 | 7.0 | V | |
| Continuous phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2) | –0.3 | VM + 0.6 | V | |
| Continuous shunt amplifier input pin voltage (AISEN, BISEN)(2) | –0.6 | 0.6 | V | |
| Peak drive current (AOUT1, AOUT2, BOUT1, BOUT2, AISEN, BISEN) | Internally limited | A | ||
| TJ | Operating junction temperature | –40 | 150 | °C |
| Tstg | Storage temperature | –65 | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Transients of ±1 V for less than 25 ns are acceptable.
6.2 ESD Ratings
| MAX | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±4000 | V |
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±1500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VM | Power supply voltage range(1) | 4 | 18 | V |
| VREF | Reference rms voltage range(3) | 1 | 3.3 | V |
| ƒPWM | Applied STEP signal | 0 | 250 | kHz |
| IVINT | VINT external load current | 1 | mA | |
| IFS | Motor full-scale current per H-bridge(2) | 0 | 1.4 | A |
| TA | Operating ambient temperature | –40 | 85 | °C |
(1) Note that RDS(ON) increases and maximum output current is reduced at VM supply voltages below 5 V
(2) Power dissipation and thermal limits must be observed
(3) Operational at VREF between 0 to 1 V, but accuracy is degraded
6.4 Thermal Information
| THERMAL METRIC(1) | DRV8846 | UNIT | |
|---|---|---|---|
| RGE (VQFN) | |||
| 24 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 34 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 36.9 | |
| RθJB | Junction-to-board thermal resistance | 12.5 | |
| ψJT | Junction-to-top characterization parameter | 0.4 | |
| ψJB | Junction-to-board characterization parameter | 12.5 | |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.5 | |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
TA = 25°C, over recommended operating conditions unless otherwise noted| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER SUPPLIES (VM, VINT) | ||||||
| VM | VM operating voltage | 4 | 18 | V | ||
| IVM | VM operating supply current | VM = 12 V, excluding winding current, nSLEEP = 1, nENBL = 0 or 1 | 3.5 | 4.5 | 5.5 | mA |
| IVMQ | VM sleep mode supply current | VM = 12 V, nSLEEP = 0, nENBL = 0 or 1 | 0.5 | 1.2 | 3 | μA |
| tSLEEP | Sleep time | nSLEEP = 0 to sleep mode | 1 | ms | ||
| tWAKE | Wake time | nSLEEP = 1 to output transition | 1 | ms | ||
| tON | Power-on time | VM > VUVLO rising to output transition | 1 | ms | ||
| VINT | VINT voltage | VM > 4 V, IOUT = 0 A to 1 mA | 3.13 | 3.3 | 3.47 | V |
| LOGIC-LEVEL INPUTS (STEP, DIR, nENBL, nSLEEP, ADEC) | ||||||
| VIL | Input logic low voltage | 0 | 0.7 | V | ||
| VIH | Input logic high voltage | 1.6 | 5.5 | V | ||
| VHYS | Input logic hysteresis | 100 | mV | |||
| IIL | Input logic low current | VIN = 0 V | –1 | 1 | μA | |
| IIH | Input logic high current | VIN = 5 V | 1 | 30 | μA | |
| RPD | Pulldown resistance | nENBL, STEP, DIR, ADEC | 200 | kΩ | ||
| nSLEEP | 500 | |||||
| tDEG | Input deglitch time | 200 | ns | |||
| tPROP | Propagation delay | STEP edge to current change | 600 | ns | ||
| TRI-LEVEL INPUTS (I0, I1, M0, M1, DEC0, DEC1, TOFF_SEL) | ||||||
| VIL | Tri-level input logic low voltage | 0 | 0.7 | V | ||
| VIZ | Tri-level input Hi-Z voltage | 1.1 | V | |||
| VIH | Tri-level input logic high voltage | 1.6 | 5.5 | V | ||
| VHYS | Tri-level input hysteresis | 100 | mV | |||
| IIL | Tri-level input logic low current | VIN = 0 V | –30 | –1 | μA | |
| IIH | Tri-level input logic high current | VIN = 5 V | 1 | 30 | μA | |
| RPD | Tri-level pulldown resistance | To GND | 170 | kΩ | ||
| RPU | Tri-level pullup resistance | To VINT | 340 | kΩ | ||
| CONTROL OUTPUTS (nFAULT) | ||||||
| VOL | Output logic low voltage | IO = 5 mA | 0.5 | V | ||
| IOH | Output logic high leakage | VO = 3.3 V | –1 | 1 | μA | |
| MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2) | ||||||
| RDS(ON) | High-side FET on resistance | VM = 12 V, I = 0.5 A, TJ = 25°C | 550 | mΩ | ||
| VM = 12 V, I = 0.5 A, TJ = 85°C(1) | 660 | |||||
| RDS(ON) | Low-side FET on resistance | VM = 12 V, I = 0.5 A, TJ = 25°C | 350 | mΩ | ||
| VM = 12 V, I = 0.5 A, TJ = 85°C(1) | 420 | |||||
| IOFF | Off-state leakage current | VM = 5 V, TJ = 25°C | –1 | 1 | μA | |
| tRISE | Output rise time | 60 | ns | |||
| tFALL | Output fall time | 60 | ns | |||
| tDEAD | Output dead time | Internal dead time | 200 | ns | ||
| PWM CURRENT CONTROL (VREF, AISEN, BISEN) | ||||||
| IREF | Externally applied VREF input current | VREF = 1 to 3.3 V | 1 | μA | ||
| VTRIP | xISEN trip voltage | For 100% current step with VREF = 3.3 V | 500 | mV | ||
| AISENSE | Current sense amplifer gain | Reference only | 6.6 | V/V | ||
| tOFF | Current control constant off time | TOFF_SEL = GND | 20 | μs | ||
| TOFF_SEL = Hi-Z | 10 | |||||
| TOFF_SEL = VINT | 30 | |||||
| PROTECTION CIRCUITS | ||||||
| VUVLO | VM undervoltage lockout | VM falling; UVLO report | 2.9 | V | ||
| VM rising; UVLO recovery | 3 | |||||
| IOCP | Overcurrent protection trip level | 2 | A | |||
| tOCP | Overcurrent deglitch time | 2.8 | μs | |||
| tRETRY | Overcurrent protection period | 1.6 | ms | |||
| TTSD | Thermal shutdown temperature | Die temperature TJ | 150 | 160 | 180 | °C |
| THYS | Thermal shutdown hysteresis | Die temperature TJ | 50 | °C | ||
(1) Not tested in production; limits are based on characterization data
6.6 Timing Requirements
TA = 25°C, over recommended operating conditions unless otherwise noted| NO. | MIN | MAX | UNIT | ||
|---|---|---|---|---|---|
| 1 | ƒSTEP | Step frequency | 250 | kHz | |
| 2 | tWH(STEP) | Pulse duration, STEP high | 1.9 | μs | |
| 3 | tWL(STEP) | Pulse duration, STEP low | 1.9 | μs | |
| 4 | tSU(STEP) | Setup time, DIR or Mx to STEP rising | 200 | ns | |
| 5 | tH(STEP) | Hold time, DIR or Mx to STEP rising | 200 | ns | |
Figure 1. Timing Diagram
6.7 Typical Characteristics
