ZHCS040D April 2011 – November 2015 DRV8843
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PWP|28
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PWP|28
訂購(gòu)信息
5 Pin Configuration and Functions
PWP Package
28-Pin HTSSOP with PowerPAD™
Top View
Pin Functions
| PIN | I/O(1) | DESCRIPTION | EXTERNAL COMPONENTS OR CONNECTIONS |
|
|---|---|---|---|---|
| NAME | PIN | |||
| POWER AND GROUND | ||||
| GND | 14, 28 | - | Device ground | |
| VMA | 4 | - | Bridge A power supply | Connect to motor supply (8.2 V to 45 V). Both pins must be connected to the same supply, bypassed with a 0.1-uF capacitor to GND, and connected to appropriate bulk capacitance. |
| VMB | 11 | - | Bridge B power supply | |
| V3P3OUT | 15 | O | 3.3-V regulator output | Bypass to GND with a 0.47-μF 6.3-V ceramic capacitor. Can be used to supply VREF. |
| CP1 | 1 | IO | Charge pump flying capacitor | Connect a 0.01-μF 50-V capacitor between CP1 and CP2. |
| CP2 | 2 | IO | Charge pump flying capacitor | |
| VCP | 3 | IO | High-side gate drive voltage | Connect a 0.1-μF 16-V ceramic capacitor and a 1-MΩ resistor to VM. |
| CONTROL | ||||
| AIN1 | 21 | I | Bridge A input 1 | Logic input controls state of AOUT1. Internal pulldown. |
| AIN2 | 20 | I | Bridge A input 2 | Logic input controls state of AOUT2. Internal pulldown. |
| AI0 | 24 | I | Bridge A current set | Sets bridge A current: 00 = 100%, 01 = 71%, 10 = 38%, 11 = 0 Internal pulldown. |
| AI1 | 25 | I | ||
| BIN1 | 22 | I | Bridge B input 1 | Logic input controls state of BOUT1. Internal pulldown. |
| BIN2 | 23 | I | Bridge B input 2 | Logic input controls state of BOUT2. Internal pulldown. |
| BI0 | 26 | I | Bridge B current set | Sets bridge B current: 00 = 100%, 01 = 71%, 10 = 38%, 11 = 0 Internal pulldown. |
| BI1 | 27 | I | ||
| DECAY | 19 | I | Decay mode | Low = slow decay, open = mixed decay, high = fast decay Internal pulldown and pullup. |
| nRESET | 16 | I | Reset input | Active-low reset input initializes internal logic and disables the H-bridge outputs. Internal pulldown. |
| nSLEEP | 17 | I | Sleep mode input | Logic high to enable device, logic low to enter low-power sleep mode. Internal pulldown. |
| AVREF | 12 | I | Bridge A current set reference input | Reference voltage for winding current set. Can be driven individually with an external DAC for microstepping, or tied to a reference (e.g., V3P3OUT). |
| BVREF | 13 | I | Bridge B current set reference input | |
| STATUS | ||||
| nFAULT | 18 | OD | Fault | Logic low when in fault condition (overtemp, overcurrent) |
| OUTPUT | ||||
| ISENA | 6 | IO | Bridge A ground / Isense | Connect to current sense resistor for bridge A |
| ISENB | 9 | IO | Bridge B ground / Isense | Connect to current sense resistor for bridge B |
| AOUT1 | 5 | O | Bridge A output 1 | Connect to motor winding A |
| AOUT2 | 7 | O | Bridge A output 2 | |
| BOUT1 | 10 | O | Bridge B output 1 | Connect to motor winding B |
| BOUT2 | 8 | O | Bridge B output 2 | |
(1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output