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SLVSA73F April 2010 – July 2014 DRV8825

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

PWP|28
- MPDS373B

散熱焊盤機械數據 (封裝 | 引腳)

PWP|28
- PPTD124Q

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
V_(VMx)	Power supply voltage	–0.3	47	V
V_(VMx)	Power supply ramp rate		1	V/µs
	Digital pin voltage	–0.5	7	V
V_(xVREF)	Input voltage	–0.3	4	V
	ISENSEx pin voltage⁽⁴⁾	–0.8	0.8	V
	Peak motor drive output current, t < 1 μs	Internally limited		A
	Continuous motor drive output current⁽³⁾	0	2.5	A
	Continuous total power dissipation	See Thermal Information
T_J	Operating junction temperature range	–40	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(3) Power dissipation and thermal limits must be observed.

(4) Transients of ±1 V for less than 25 ns are acceptable

7.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–60	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	–2000	2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	–500	500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

		MIN	MAX	UNIT
V_(VMx)	Motor power supply voltage range⁽¹⁾	8.2	45	V
V_(VREF)	VREF input voltage⁽²⁾	1	3.5	V
I_V3P3	V3P3OUT load current	0	1	mA

(1) All V_M pins must be connected to the same supply voltage.

(2) Operational at VREF between 0 to 1 V, but accuracy is degraded.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		DRV8825	UNIT
		PWP
		28 PINS
R_θJA	Junction-to-ambient thermal resistance⁽²⁾	31.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance⁽³⁾	15.9
R_θJB	Junction-to-board thermal resistance⁽⁴⁾	5.6
ψ_JT	Junction-to-top characterization parameter⁽⁵⁾	0.2
ψ_JB	Junction-to-board characterization parameter⁽⁶⁾	5.5
R_θJC(bot)	Junction-to-case (bottom) thermal resistance⁽⁷⁾	1.4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

7.5 Electrical Characteristics

over operating free-air temperature range of –40°C to 85°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLIES
I_VM	VM operating supply current	V_(VMx) = 24 V		5	8	mA
I_VMQ	VM sleep mode supply current	V_(VMx) = 24 V		10	20	μA
V3P3OUT REGULATOR
V_3P3	V3P3OUT voltage	IOUT = 0 to 1 mA	3.2	3.3	3.4	V
LOGIC-LEVEL INPUTS
V_IL	Input low voltage		0		0.7	V
V_IH	Input high voltage		2.2		5.25	V
V_HYS	Input hysteresis		0.3	0.45	0.6	V
I_IL	Input low current	VIN = 0	–20		20	μA
I_IH	Input high current	VIN = 3.3 V			100	μA
R_PD	Internal pulldown resistance			100		kΩ
nHOME, nFAULT OUTPUTS (OPEN-DRAIN OUTPUTS)
V_OL	Output low voltage	I_O = 5 mA			0.5	V
I_OH	Output high leakage current	V_O = 3.3 V			1	μA
DECAY INPUT
V_IL	Input low threshold voltage	For slow decay mode			0.8	V
V_IH	Input high threshold voltage	For fast decay mode	2			V
I_IN	Input current		–40		40	µA
R_PU	Internal pullup resistance (to 3.3 V)			130		kΩ
R_PD	Internal pulldown resistance			80		kΩ
H-BRIDGE FETS
R_DS(ON)	HS FET on resistance	V_(VMx) = 24 V, I_O = 1 A, T_J = 25°C		0.2		Ω
	HS FET on resistance	V_(VMx) = 24 V, I_O = 1 A, T_J = 85°C		0.25	0.32
	LS FET on resistance	V_(VMx) = 24 V, I_O = 1 A, T_J = 25°C		0.2
	LS FET on resistance	V_(VMx) = 24 V, I_O = 1 A, T_J = 85°C		0.25	0.32
I_OFF	Off-state leakage current		–20		20	μA
MOTOR DRIVER
ƒ_PWM	Internal current control PWM frequency			30		kHz
t_BLANK	Current sense blanking time			4		μs
t_R	Rise time		30		200	ns
t_F	Fall time		30		200	ns
PROTECTION CIRCUITS
V_UVLO	VM undervoltage lockout voltage	V_(VMx) rising		7.8	8.2	V
I_OCP	Overcurrent protection trip level		3			A
t_DEG	Overcurrent deglitch time			3		µs
t_TSD	Thermal shutdown temperature	Die temperature	150	160	180	°C
CURRENT CONTROL
I_REF	xVREF input current	V_(xVREF) = 3.3 V	–3		3	μA
V_TRIP	xISENSE trip voltage	V_(xVREF) = 3.3 V, 100% current setting	635	660	685	mV
ΔI_TRIP	Current trip accuracy (relative to programmed value)	V_(xVREF) = 3.3 V, 5% current setting	–25%		25%
		V_(xVREF) = 3.3 V, 10% to 34% current setting	–15%		15%
		V_(xVREF) = 3.3 V, 38% to 67% current setting	–10%		10%
		V_(xVREF) = 3.3 V, 71% to 100% current setting	–5%		5%
A_ISENSE	Current sense amplifier gain	Reference only		5		V/V

7.6 Timing Requirements

			MIN	MAX	UNIT
1	ƒ_STEP	Step frequency		250	kHz
2	t_WH(STEP)	Pulse duration, STEP high	1.9		μs
3	t_WL(STEP)	Pulse duration, STEP low	1.9		μs
4	t_SU(STEP)	Setup time, command before STEP rising	650		ns
5	t_H(STEP)	Hold time, command after STEP rising	650		ns
6	t_ENBL	Enable time, nENBL active to STEP	650		ns
7	t_WAKE	Wakeup time, nSLEEP inactive high to STEP input accepted		1.7	ms