SLVSA73F April 2010 – July 2014 DRV8825
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Simplified Schematic
- 5 Revision History
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- PWP|28
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- PWP|28
訂購信息
7 Specifications
7.1 Absolute Maximum Ratings(1)(2)
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| V(VMx) | Power supply voltage | –0.3 | 47 | V | |
| Power supply ramp rate | 1 | V/µs | |||
| Digital pin voltage | –0.5 | 7 | V | ||
| V(xVREF) | Input voltage | –0.3 | 4 | V | |
| ISENSEx pin voltage(4) | –0.8 | 0.8 | V | ||
| Peak motor drive output current, t < 1 μs | Internally limited | A | |||
| Continuous motor drive output current(3) | 0 | 2.5 | A | ||
| Continuous total power dissipation | See Thermal Information | ||||
| TJ | Operating junction temperature range | –40 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Power dissipation and thermal limits must be observed.
(4) Transients of ±1 V for less than 25 ns are acceptable
7.2 Handling Ratings
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| Tstg | Storage temperature range | –60 | 150 | °C | |
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | –2000 | 2000 | V |
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | –500 | 500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| V(VMx) | Motor power supply voltage range(1) | 8.2 | 45 | V | |
| V(VREF) | VREF input voltage(2) | 1 | 3.5 | V | |
| IV3P3 | V3P3OUT load current | 0 | 1 | mA | |
(1) All VM pins must be connected to the same supply voltage.
(2) Operational at VREF between 0 to 1 V, but accuracy is degraded.
7.4 Thermal Information
| THERMAL METRIC(1) | DRV8825 | UNIT | |
|---|---|---|---|
| PWP | |||
| 28 PINS | |||
| RθJA | Junction-to-ambient thermal resistance(2) | 31.6 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance(3) | 15.9 | |
| RθJB | Junction-to-board thermal resistance(4) | 5.6 | |
| ψJT | Junction-to-top characterization parameter(5) | 0.2 | |
| ψJB | Junction-to-board characterization parameter(6) | 5.5 | |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance(7) | 1.4 | |
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
7.5 Electrical Characteristics
over operating free-air temperature range of –40°C to 85°C (unless otherwise noted)7.6 Timing Requirements
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| 1 | ƒSTEP | Step frequency | 250 | kHz | |
| 2 | tWH(STEP) | Pulse duration, STEP high | 1.9 | μs | |
| 3 | tWL(STEP) | Pulse duration, STEP low | 1.9 | μs | |
| 4 | tSU(STEP) | Setup time, command before STEP rising | 650 | ns | |
| 5 | tH(STEP) | Hold time, command after STEP rising | 650 | ns | |
| 6 | tENBL | Enable time, nENBL active to STEP | 650 | ns | |
| 7 | tWAKE | Wakeup time, nSLEEP inactive high to STEP input accepted | 1.7 | ms | |
Figure 1. Timing Diagram
7.7 Typical Characteristics
