亚洲第一av片精品堂在线观看,久久婷婷五月综合国产尤物APP ,亚洲精品tv久久久久久久久

ZHCSCE6 April 2014 DRV8824-Q1

PRODUCTION DATA.

封裝選項(xiàng)

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾⁽²⁾

		VALUE	UNIT
VMx	Power supply voltage range	–0.3 to 47	V
	Digital terminal voltage range	–0.5 to 7	V
VREF	Input voltage	–0.3 to 4	V
	ISENSEx terminal voltage	–0.3 to 0.8	V
	Peak motor drive output current, t < 1 μS	Internally limited	A
	Continuous motor drive output current⁽³⁾	1.6	A
	Continuous total power dissipation	See Thermal Information table
T_J	Operating virtual junction temperature range	–40 to 150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(3) Power dissipation and thermal limits must be observed.

7.2 Handling Ratings

		MIN	MAX	UNIT
T_stg	Storage temperature range	–60	150	°C
V_ESD	HBD (human body model), AEC-Q100 Classification H2		2000	V
V_ESD	CDM (charged device model), AEC-Q100 Classification C4B		750	V

7.3 Recommended Operating Conditions

		MIN	MAX	UNIT
V_M	Motor power supply voltage⁽¹⁾	8.2	45	V
V_REF	VREF input voltage⁽²⁾	1	3.5	V
I_V3P3	V3P3OUT load current		1	mA

(1) All V_M terminals must be connected to the same supply voltage.

(2) Operational at VREF between 0 V and 1 V, but accuracy is degraded.

7.4 Thermal Information

THERMAL METRIC		DRV8824-Q1	UNIT
		PWP
		28 TERMINAL
R_θJA	Junction-to-ambient thermal resistance⁽¹⁾	38.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance⁽²⁾	23.3
R_θJB	Junction-to-board thermal resistance⁽³⁾	21.2
ψ_JT	Junction-to-top characterization parameter⁽⁴⁾	0.8
ψ_JB	Junction-to-board characterization parameter⁽⁵⁾	20.9
R_θJC(bot)	Junction-to-case (bottom) thermal resistance⁽⁶⁾	2.6

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(4) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(5) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

7.5 Electrical Characteristics

over operating free-air temperature range of -40°C to 125°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLIES
I_VM	VM operating supply current	V_M = 24 V, f_PWM < 50 kHz		5	8	mA
I_VMQ	VM sleep mode supply current	V_M = 24 V		10	20	μA
V_UVLO	VM undervoltage lockout voltage	V_M rising		7.8	8.2	V
V3P3OUT REGULATOR
V_3P3	V3P3OUT voltage	IOUT = 0 to 1 mA, V_M = 24 V, T_J = 25°C	3.18	3.30	3.45	V
V_3P3	V3P3OUT voltage	IOUT = 0 to 1 mA	3.10	3.30	3.50	V
LOGIC-LEVEL INPUTS
V_IL	Input low voltage			0.6	0.7	V
V_IH	Input high voltage		2		5.25	V
V_HYS	Input hysteresis			0.45		V
I_IL	Input low current	VIN = 0	–20		20	μA
I_IH	Input high current	VIN = 3.3 V			100	μA
R_PD	Internal pulldown resistance	nENBL, nRESET, DIR, STEP, MODEx		100		kΩ
R_PD	Internal pulldown resistance	nSLEEP		1		MΩ
nHOME, nFAULT OUTPUTS (OPEN-DRAIN OUTPUTS)
V_OL	Output low voltage	I_O = 5 mA			0.5	V
I_OH	Output high leakage current	V_O = 3.3 V			1	μA
DECAY INPUT
V_IL	Input low threshold voltage	For slow decay mode			0.8	V
V_IH	Input high threshold voltage	For fast decay mode	2			V
I_IN	Input current		–100		100	µA
R_PU	Internal pullup resistance			130		kΩ
R_PD	Internal pulldown resistance			80		kΩ
H-BRIDGE FETS
R_DS(ON)	HS FET on resistance	V_M = 24 V, I_O = 1 A, T_J = 25°C		0.63		Ω
		V_M = 24 V, I_O = 1 A, T_J = 85°C		0.76	0.90
		V_M = 24 V, I_O = 1 A, T_J = 125°C		0.85	1
R_DS(ON)	LS FET on resistance	V_M = 24 V, I_O = 1 A, T_J = 25°C		0.65		Ω
		V_M = 24 V, I_O = 1 A, T_J = 85°C		0.78	0.90
		V_M = 24 V, I_O = 1 A, T_J = 125°C		0.85	1
I_OFF	Off-state leakage current		–20		20	μA
MOTOR DRIVER
f_PWM	Internal PWM frequency			50		kHz
t_BLANK	Current sense blanking time			3.75		μs
t_R	Rise time	V_M = 24 V	100		360	ns
t_F	Fall time	V_M = 24 V	80		250	ns
t_DEAD	Dead time			400		ns
PROTECTION CIRCUITS
I_OCP	Overcurrent protection trip level		1.8		5	A
t_TSD	Thermal shutdown temperature	Die temperature	150	160	180	°C
CURRENT CONTROL
I_REF	xVREF input current	xVREF = 3.3 V	–3		3	μA
V_TRIP	xISENSE trip voltage	xVREF = 3.3 V, 100% current setting	635	660	685	mV
ΔI_TRIP	Current trip accuracy (relative to programmed value)	xVREF = 3.3 V , 5% current setting	–25%		25%
		xVREF = 3.3 V , 10% - 34% current setting	–15%		15%
		xVREF = 3.3 V, 38% - 67% current setting	–10%		10%
		xVREF = 3.3 V, 71% - 100% current setting	–5%		5%
A_ISENSE	Current sense amplifier gain	Reference only		5		V/V

7.6 Timing Requirements

			MIN	MAX	UNIT
1	f_STEP	Step frequency		250	kHz
2	t_WH(STEP)	Pulse duration, STEP high	1.9		μs
3	t_WL(STEP)	Pulse duration, STEP low	1.9		μs
4	t_SU(STEP)	Setup time, command to STEP rising	200		ns
5	t_H(STEP)	Hold time, command to STEP rising	200		ns
6	t_ENBL	Enable time, nENBL active to STEP	200		ns
7	t_WAKE	Wakeup time, nSLEEP inactive to STEP	1		ms