ZHCSG08E October 2016 – January 2021 DRV8702-Q1 , DRV8703-Q1
PRODUCTION DATA
| PIN | TYPE(1) | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | NO. | |||
| DRV8702-Q1 | DRV8703-Q1 | |||
| AVDD | 14 | 14 | PWR | Analog regulator. This pin is the 5-V analog supply regulator. Bypass this pin to ground with a 6.3-V, 1-μF ceramic capacitor. |
| CPH | 30 | 30 | PWR | Charge-pump switching node. Connect a 0.1-μF X7R capacitor rated for the supply voltage (VM) between the CPH and CPL pins. |
| CPL | 31 | 31 | PWR | Charge-pump switching node. Connect a 0.1-μF X7R capacitor rated for the supply voltage (VM) between the CPH and CPL pins. |
| DVDD | 12 | 12 | PWR | Logic regulator. This pin is the regulator for the 3.3-V logic supply. Bypass this pin to ground with a 6.3-V, 1-μF ceramic capacitor. |
| GH1 | 18 | 18 | O | High-side gate. Connect this pin to the high-side FET gate. |
| GH2 | 26 | 26 | O | High-side gate. Connect this pin to the high-side FET gate. |
| GL1 | 20 | 20 | O | Low-side gate. Connect this pin to the low-side FET gate. |
| GL2 | 24 | 24 | O | Low-side gate. Connect this pin to the low-side FET gate. |
| GND | 1 | 1 | PWR | Device ground. Connect this pin to the system ground. |
| GND | 13 | 13 | PWR | Device ground. Connect this pin to the system ground. |
| GND | 17 | 17 | PWR | Device ground. Connect this pin to the system ground. |
| GND | 4 | — | PWR | Device ground. Connect this pin to the system ground. |
| GND | 7 | — | PWR | Device ground. Connect this pin to the system ground. |
| GND | 9 | — | PWR | Device ground. Connect this pin to the system ground. |
| IDRIVE | 5 | — | I | Current setting pin for the gate drive. The resistor value or voltage forced on this pin sets the gate-drive current. For more information see the GUID-8CC6FA8E-2B74-48FE-8D23-FE1EDB0E56CF.html#GUID-8CC6FA8E-2B74-48FE-8D23-FE1EDB0E56CF section. |
| IN1/PH | 2 | 2 | I | Input control pins. The logic of this pin is dependent on the MODE pin. This pin is connected to an internal pulldown resistor. |
| IN2/EN | 3 | 3 | I | Input control pins. The logic of this pin is dependent on the MODE pin. This pin is connected to an internal pulldown resistor. |
| MODE | 11 | 11 | I | Mode control pin. Pull this pin to logic low to use H-bridge operation. Pull this pin to logic high for independent half-bridge operation. This pin is connected to an internal resistor divider. Operation of this pin is latched on power up or when exiting sleep mode. This pin is connected to an internal pullup and pulldown resistors. |
| NC | 32 | 32 | NC | No connect. No internal connection. |
| SCLK | — | 7 | I | SPI clock. This pin is for the SPI clock signal. This pin is connected to an internal pulldown resistor. |
| SDI | — | 6 | I | SPI input. This pin is for the SPI input signal. This pin is connected to an internal pulldown resistor. |
| SDO | — | 4 | OD | SPI output. This pin is for the SPI output signal. This pin is an open-drain output that requires an external pullup resistor. |
| SH1 | 19 | 19 | I | High-side source. Connect this pin to the high-side FET source. |
| SH2 | 25 | 25 | I | High-side source. Connect this pin to the high-side FET source |
| SL2 | 23 | 23 | I | Low-side source. Connect this pin to the low-side FET source. |
| SN | 22 | 22 | I | Shunt-amplifier negative input. Connect this pin to the current-sense resistor. |
| SO | 16 | 16 | O | Shunt-amplifier output. The voltage on this pin is equal to the SP voltage times AV plus an offset. Place no more than 1 nF of capacitance on this pin. |
| SP | 21 | 21 | I | Shunt-amplifier positive input. Connect this pin to the current-sense resistor. |
| VCP | 29 | 29 | PWR | Charge-pump output. Connect a 16-V, 1-μF ceramic capacitor between this pin and the VM pin. |
| VDRAIN | 27 | 27 | I | High-side FET drain connection. This pin is common for the two H-bridges. |
| VDS | 6 | — | I | VDS monitor setting pin. The resistor value or voltage forced on this pin sets the VDS monitor threshold. For more information see the GUID-091029B6-7474-4E2E-8364-A029B649E362.html#GUID-091029B6-7474-4E2E-8364-A029B649E362 section. |
| VM | 28 | 28 | PWR | Power supply. Connect this pin to the motor supply voltage. Bypass this pin to ground with a 0.1-μF ceramic plus a 10-μF (minimum) capacitor. |
| VREF | 15 | 15 | I | Current set reference input. The voltage on this pin sets the driver chopping current. |
| nWDFLT | — | 9 | OD | Watchdog fault indication pin. This pin is pulled logic low when a watchdog fault condition occurs. This pin is an open-drain output that requires an external pullup resistor. |
| nFAULT | 10 | 10 | OD | Fault indication pin. This pin is pulled logic low when a fault condition occurs. This pin is an open-drain output that requires an external pullup resistor. |
| nSCS | — | 5 | I | SPI chip select. This pin is the select and enable for SPI. This pin is active low. |
| nSLEEP | 8 | 8 | I | Device sleep mode. Pull this pin to logic low to put device into a low-power sleep mode with the FETs in high impedance (Hi-Z). This pin is connected to an internal pulldown resistor. |