ZHCSR87 December 2022 DRV8316C
PRODUCTION DATA
| PIN | 40-pin Package | TYPE(1) | DESCRIPTION | |
|---|---|---|---|---|
| NAME | DRV8316CR | DRV8316CT | ||
| AGND | 2, 26 | 2, 26 | GND | Device analog ground. Refer Section 11.1 for connections recommendation. |
| AVDD | 25 | 25 | PWR O | 3.3-V internal regulator output. Connect an X5R or X7R, 1-μF, 6.3-V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 30 mA externally. |
| CP | 8 | 8 | PWR O | Charge pump output. Connect a X5R or X7R, 1-μF, 16-V ceramic capacitor between the CP and VM pins. |
| CPH | 7 | 7 | PWR | Charge pump switching node. Connect a X5R or X7R, 47-nF, ceramic capacitor between the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device. |
| CPL | 6 | 6 | PWR | |
| DRVOFF | 21 | 21 | I | When this pin is pulled high the six MOSFETs in the power stage are turned OFF making all outputs Hi-Z. |
| FB_BK | 3 | 3 | PWR I | Feedback for buck regulator. Connect to buck regulator output after the inductor/resistor. |
| GAIN | — | 36 | I | Amplifier gain setting. The pin is a 4-level input pin set by an external resistor. |
| GND_BK | 4 | 4 | GND | Buck regulator ground. Refer Section 11.1 for connections recommendation. |
| INHA | 27 | 27 | I | High-side driver control input for OUTA. This pin controls the output of the high-side MOSFET. |
| INHB | 29 | 29 | I | High-side driver control input for OUTB. This pin controls the output of the high-side MOSFET. |
| INHC | 31 | 31 | I | High-side driver control input for OUTC. This pin controls the output of the high-side MOSFET. |
| INLA | 28 | 28 | I | Low-side driver control input for OUTA. This pin controls the output of the low-side MOSFET. |
| INLB | 30 | 30 | I | Low-side driver control input for OUTB. This pin controls the output of the low-side MOSFET. |
| INLC | 32 | 32 | I | Low-side driver control input for OUTC. This pin controls the output of the low-side MOSFET. |
| MODE | — | 33 | I | PWM input mode setting. This pin is a 4-level input pin set by an external resistor. |
| NC | 1, 24 | 1 | — | No connection, open |
| nFAULT | 22 | 22 | O | Fault indicator. Pulled logic-low with fault condition; Open-drain output requires an external pull-up resistor to 1.8 V to 5.0 V. If external supply is used to pull up nFAULT, ensure that it is pulled to >2.2 V on power up or the device will enter test mode |
| nSCS | 36 | — | I | Serial chip select. A logic low on this pin enables serial interface communication. |
| nSLEEP | 23 | 23 | I | Driver nSLEEP. When this pin is logic low, the device goes into a low-power sleep mode. A 20 to 40-μs low pulse can be used to reset fault conditions without entering sleep mode. |
| OCP/SR | — | 35 | I | OCP level and Synchronous Rectification (Active Demagnetization) setting. This pin is a 4-level input pin set by an external resistor. |
| OUTA | 13, 14 | 13, 14 | PWR O | Half bridge output A |
| OUTB | 16, 17 | 16, 17 | PWR O | Half bridge output B |
| OUTC | 19, 20 | 19, 20 | PWR O | Half bridge output C |
| PGND | 12, 15, 18 | 12, 15, 18 | GND | Device power ground. Refer Section 11.1 for connections recommendation. |
| SCLK | 35 | — | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin (SPI devices). |
| SDI | 34 | — | I | Serial data input. Data is captured on the falling edge of the SCLK pin (SPI devices). |
| SDO | 33 | — | O | Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor (SPI devices). |
| SLEW | — | 34 | I | Slew rate control setting. This pin is a 4-level input pin set by an external resistor. |
| SOA | 40 | 40 | O | Current sense amplifier output. Supports capacitive load or low pass filter (resistor in series and capacitor to GND) |
| SOB | 39 | 39 | O | Current sense amplifier output. Supports capacitive load or low pass filter (resistor in series and capacitor to GND) |
| SOC | 38 | 38 | O | Current sense amplifier output. Supports capacitive load or low pass filter (resistor in series and capacitor to GND) |
| SW_BK | 5 | 5 | PWR O | Buck switch node. Connect this pin to an inductor or resistor. |
| VM | 9, 10, 11 | 9, 10, 11 | PWR I | Power supply. Connect to motor supply voltage; bypass to PGND with two 0.1-μF capacitors (for each pin) plus one bulk capacitor rated for VM. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device. |
| VSEL_BK | — | 24 | I | Buck output voltage setting. This pin is a 4-level input pin set by an external resistor. |
| VREF/ILIM | 37 | 37 | PWR/I | VREF in PWM Mode 1 and Mode 3:
Current sense amplifier power supply input and reference. Connect a X5R or X7R,
0.1-μF, 6.3-V ceramic capacitor between the VREF and AGND pins. ILIM in PWM Mode 2 and Mode 4: Sets the threshold for phase current used in cycle by cycle current limit. |
| Thermal pad | GND | Must be connected to analog ground. | ||