SPI Format - with Parity

The SDI input data word is 24 bits long and consists of the following format:

• 1 read or write bit, W (bit B23)
• 6 address bits, A (bits B22 through B17)
• Parity bit, P (bit B16)
• 15 data bits with 1 parity bit, D (bits B15 through B0)

The SDO output data word is 24 bits long. The most significant bits are status bits and the least significant 16 bits are the data content of the register being accessed.

tSPI Format - with Parity

The SDI input data word is 32 bits long and consists of the following format:

• 1 read or write bit, W (bit B31)
• 4 secondary device ID bits, AD (bits B30 through B27)
• 8 address bits, A (bits B26 through B19)
• 2 reserved bits, 0 (bits B18, bit B17)
• Parity bit, P (bit B16)
• 15 data bits with 1 parity bit, D (bits B15 through B0)

The SDO output data word is 24 bits long. The first 8 bits are status bits and the last 16 bits are the data content of the register being accessed. The format is same as standard SPI shown in Table 8-8

The details of the bits used in SPI and tSPI frame format are detailed below.

Read/Write Bit (R/W) : R/W (W0) bit being 0 indicates a SPI/tSPI Write transaction. For a read operation RW bit needs to be 1.

Secondary device ID Bits (AD) : Each tSPI secondary device on the same chip select should have a unique identifier. Secondary device ID field is the 4-bit unique identifier of the tSPI secondary device. For a successful Read/Write transaction the secondary device ID field should match with the secondary device address. In DRV8311 the two most significant bits of secondary device addresses are set to 00. The least two significant bits of the secondary device address can be configured using the AD1 and AD0 pins. The secondary device address 15 (0xF) is reserved for general call, all the devices on the same bus accept a write operation when the secondary device ID field is set to 15. Hence the valid tSPI secondary device addresses for DRV8311 range from 0 to 3 and 15 (general call address).

Address Bits (A) : A tSPI secondary device takes 8-bit register address whereas SPI secondary device takes 6-bit register address. Each tSPI secondary device has two dedicated 8-bit address pointers, one for read and one for write. During a sequential read transaction, the read address pointer gets incremented automatically. During a sequential write transaction, both write address pointer and read address pointer will be incremented automatically.

Parity Bit (P) : Both header and data fields of a SPI/tSPI input data frame include a parity bit for single bit error detection. The parity scheme used is even parity i.e., the number of ones in a block of 16-bits (including the parity bit) is even. Data will be written to the internal registers only if the parity check is successful. During a read operation, the tSPI secondary device inserts a parity bit at the MSB of read data. Parity checks can be enabled or disabled by configuring the SPI_PEN bit of SYS_CTRL register. Parity checks are disabled by default.

Error Handling

Parity Error: Upon detecting a parity error, the secondary device responds in the following ways. Parity error gets latched and reported on nFAULT. The error status is available for read on SPI_PARITY field of SYS_STS register. A parity error in the header will not prevent the secondary device from responding with data. The SDO will be driven by the secondary device being addressed. Updates to write address pointer and the device registers will be ignored when parity error is detected. In a sequential write, upon detection of parity error any subsequent register writes will be ignored.

Frame Error :Any incomplete tSPI Frame will be reported as Frame error. If the number of tSPI clock cycles is not a multiple of 16, then the transfer is considered to be incomplete. Frame errors will be latched in FRM_ERR field of SYS_STS register and indicated on nFAULT.

SPI Read / Write Sequence

SPI Read Sequence: The SPI read transaction comprises of an 8-bit header (R/W - 1 bit, Address - 6 bits, and party -1 bit) followed by 16-bit dummy data words. Upon receiving the first byte of header, the secondary device responds with an 8-bit device status information. The read address pointer gets updated immediately after receiving the address field of the header. The read address from the header acts as the starting address for the register reads. The read address pointer gets incremented automatically upon completion of a 16-bit transfer. The length of data transfer is not restricted by the secondary device. The secondary device responds with data as long as the primary device transmits dummy words. If parity error check is enabled, the MSB of read data will be replaced with computed parity bit

SPI Write Sequence: SPI write transaction comprises of an 8-bit header followed by 16-bit data words to be written into the register bank. Similar to a read transaction, the addressed secondary device responds with an 8-bit device status information upon receiving the first byte of header. Once the header bytes are received, the write address pointer gets updated. The write address from the header acts as the starting address for sequential register writes. The read address pointer will retain the address of the register being read in the previous tSPI transaction. The length of data transfer is not restricted by the secondary device. Both read and write address pointers will be incremented automatically upon completion of a 16-bit transfer. While receiving data from the primary device, the SDO will be driven with the register data addressed by read address pointer.

tSPI Communication Sequence

The tSPI interface is similar to regular SPI interface in functionality but add support for multiple devices under the same Chip Select (nSCS). Any existing SPI primary device would be able to communicate with the tSPI secondary devices with modifications in the frame format. A valid tSPI frame must meet the following conditions (similar to SPI interface):

• The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high. A high to low transition at the nSCS pin is the start of frame and a low to high transition is the end of the frame.
• When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is placed in the Hi-Z state.
• Data is captured on the falling edge of the SCLK signal and data is driven on the rising edge of the SCLK signal.
• The most significant bit (MSB) is shifted in and out first.
• A minimum of 16 SCLK cycles must occur for transaction to be valid & the number of SCLK cycles in a single transaction must me a multiple of 16.
• If the data word sent to the SDI pin is not a multiple of 16 bits, a frame error occurs and the excess SCLK cycles are ignored.

Figure 8-34 tSPI Block Diagram with Multiple Devices on Same Chip Select

Figure 8-35 tSPI with PWM_SYNC

tSPI Read Sequence: A tSPI read transaction has a 16-bit header (R/W - 1 bit, Secondary device ID - 4 bits, Address - 8 bits, reserved -2 bits and party -1 bit) followed by 16-bit dummy data words. Upon receiving the first byte of header, the secondary device being addressed with matching secondary device ID field (configured using AD0 and AD1 pins), responds with an 8-bit device status information. The read address from the header acts as the starting address for the register reads. The address gets incremented automatically upon completion of a 16-bit transfer. The length of data transfer is not restricted by the secondary device. The secondary device responds with data as long as the primary device transmits dummy words. If parity error check is enabled, the MSB of read data will be replaced with computed parity bit.

tSPI Write Sequence: A tSPI write transaction has a 16-bit header followed by 16-bit data words to be written into the register bank. Similar to a read transaction, the addressed secondary device responds with an 8-bit device status information upon receiving the first byte of header. The write address from the header acts as the starting address for sequential register writes. The length of data transfer is not restricted by the secondary device. Both write and read address pointers will be incremented automatically upon completion of a 16-bit transfer. While receiving data from the primary device, the SDO will be driven with the register data addressed by read address pointer

tSPI Read Address Update Sequence: The independent read and write address pointers in the secondary device would allow reading data from one set of registers while writing data to another set of registers. To achieve this, the primary device should first send a read address update frame before the tSPI write transaction. A read address frame is nothing but just the tSPI read sequence with just the header. The first tSPI transaction updates the read address pointer to desired register address. The second tSPI transaction is a register write sequence. During this sequence, the data send on SDO by the secondary device will be from the register pointed by read address pointer which was initialized in the previous tSPI read sequence.

The tSPI read/write sequence with parity is shown in Figure 8-36. The SPI frame header is marked as CMD[15:8] and CMD[7:0].