| VM SUPPLY |
| IVM |
VM active current |
ENABLE = active, VREG and VSW open |
|
12 |
18 |
mA |
| ISTBY |
VM standby current |
ENABLE = inactive |
|
|
120 |
µA |
| VRESET |
VM logic reset voltage |
VM falling |
|
|
4.6 |
V |
| VM rising |
5 |
|
|
| VREG SUPPLY |
| VVREG |
Output voltage |
IOUT = 1 to 30 mA |
4.75 |
5 |
5.25 |
V |
| IVREG |
Output current |
|
|
|
30 |
mA |
| VSW SUPPLY |
| RDS(ON) |
VSW switch on-resistance |
IOUT = 1 to 30 mA |
|
9 |
20 |
Ω |
| IVSW |
Output current |
|
|
|
30 |
mA |
| INTERNAL CLOCK OSCILLATOR |
| fCLK50 |
Internal CLK50 clock frequency |
|
|
50 |
|
MHz |
| LOGIC-LEVEL INPUTS AND OUTPUTS |
| VIL |
Low-level input voltage |
|
|
|
0.8 |
V |
| VIH |
High-level input voltage |
|
1.5 |
|
5.5 |
V |
| IIL |
Low-level input current |
|
–50 |
|
50 |
µA |
| IIH |
High-level input current |
VIN = 3.3 V, RESET, DIR, BRAKE, CLKIN, SCS, SCLK, SDATAI, SMODE |
20 |
|
100 |
µA |
| VIN = 3.3 V, ENABLE |
6 |
|
9 |
| VHYS |
Input hysteresis voltage |
|
0.1 |
0.3 |
0.5 |
V |
| RPD |
Input pulldown resistance |
RESET, DIR, BRAKE, CLKIN, SCS, SCLK, SDATAI, SMODE |
50 |
100 |
150 |
kΩ |
| ENABLE |
350 |
|
550 |
| OPEN DRAIN OUTPUTS |
| VOL |
Low-level output voltage |
IOUT = 2.0 mA |
|
|
0.5 |
V |
| IOH |
Output leakage current |
VOUT = 3.3 V |
|
|
1 |
µA |
| FG AMPLIFIER AND COMPARATOR |
| VIO |
FG amplifier input offset voltage |
|
–7 |
|
7 |
mV |
| IIB |
FG amplifier input bias current |
|
–1 |
|
1 |
μA |
| VICM |
FG amplifier input common mode voltage range |
|
1.5 |
|
3.5 |
V |
| AV |
FG amplifier open loop voltage gain |
|
45 |
|
|
dB |
| GBW |
FG amplifier gain bandwidth product |
|
500 |
|
|
kHz |
| VREF+ |
FG comparator positive reference voltage |
|
–20% |
VVREG / 2 |
20% |
V |
| VIT+ |
FG comparator positive threshold |
|
–20% |
VVREG / 1.8 |
20% |
V |
| VIT- |
FG comparator negative threshold |
|
–20% |
VVREG / 2 |
20% |
V |
| HALL SENSOR INPUTS |
| VHYS |
Hall amplifier hysteresis voltage |
|
15 |
20 |
25 |
mV |
| ?VHYS |
Hall amplifier hysteresis difference |
Between U, V, W |
–5 |
|
5 |
mV |
| VID |
Hall amplifier input differential |
|
50 |
|
|
mV |
| VCM |
Hall amplifier input common mode voltage range |
|
1.5 |
|
3.5 |
V |
| IIN |
Input leakage current |
H_x+ = H_x- |
–10 |
|
10 |
μA |
| tHDEG |
Hall deglitch time |
|
|
20 |
|
μs |
| MOSFET DRIVERS |
| VOUTH |
High-side gate drive output voltage |
IO = 100 μA, VM ≥ 12V |
|
VM + 10 |
|
V |
| VOUTL |
Low-side gate drive output voltage |
IO = 100 μA |
|
10 |
|
V |
| IOUT |
Peak gate drive current |
IDRIVE = 000 |
|
10 |
|
mA |
| IDRIVE = 001 |
|
20 |
|
| IDRIVE = 010 |
|
30 |
|
| IDRIVE = 011 |
|
50 |
|
| IDRIVE = 100 |
|
90 |
|
| IDRIVE = 101 |
|
100 |
|
| IDRIVE = 110 |
|
110 |
|
| IDRIVE = 111 |
|
130 |
|
| CYCLE-BY-CYCLE CURRENT LIMITER |
| VLIMITER |
Voltage limit across RISENSE for the current limiter |
|
0.225 |
0.25 |
0.275 |
V |
| tBLANK |
Time that VLIMITER is ignored, from the start of the PWM cycle |
OCPDEG = 00 |
|
2 |
|
µs |
| OCPDEG = 01 |
|
3 |
|
| OCPDEG = 10 |
|
3.75 |
|
| OCPDEG = 11 |
|
6 |
|
| PROTECTION CIRCUITS |
| VSENSEOCP |
Voltage limit across RISENSE for overcurrent protection |
|
1.7 |
1.8 |
1.9 |
V |
| VFETOCP |
Voltage limit across each external FET’s drain to source for overcurrent protection |
OCPTH = 00 |
200 |
250 |
400 |
mV |
| OCPTH = 01 |
400 |
500 |
600 |
| OCPTH = 10 |
600 |
750 |
850 |
| OCPTH = 11 |
850 |
1000 |
1200 |
| tOCP |
Deglitch time for VSENSEOCP or VFETOCP to trigger |
OCPDEG = 00 |
|
1.6 |
|
µs |
| OCPDEG = 01 |
|
2.3 |
|
| OCPDEG = 10 |
|
3 |
|
| OCPDEG = 11 |
|
5 |
|
| VUVLO |
VM undervoltage lockout |
VM rising |
|
8 |
|
V |
| VM falling |
|
7.8 |
|
| VOVLO |
VM overvoltage lockout |
VM rising, OVTH = 0 |
32 |
34.5 |
36 |
V |
| VM rising, OVTH = 1 |
|
28 |
29 |
| tRETRY |
Fault retry time after OTS |
RETRY = 1 |
|
5 |
|
s |
| TTSD |
Thermal shutdown die temperature |
|
150 |
160 |
|
°C |
| VCPFAIL |
VCP failure threshold (CPFAIL bit) |
|
|
VM + 3 |
|
V |