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ZHCSC39B February 2014 – November 2017 DRV8308

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RHA|40
- MPQF135D

散熱焊盤機械數據 (封裝 | 引腳)

RHA|40
- QFND227K

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted) ⁽¹⁾ ⁽²⁾ ⁽³⁾

	MIN	MAX	UNIT
Power supply voltage (VM)	–0.3	42	V
Charge pump and high side gate drivers (VCP, UHSG, VHSG, WHSG)	–0.3	50	V
Output pin, low side gate drivers, charge pump flying cap and switched VM power supply voltage (U, V, W, ULSG, VLSG, WLSG, CP1, CP2 VSW)	–0.6	40	V
Internal core voltage regulator (VINT)	–0.3	2	V
Linear voltage regulator output (VREG)	–0.3	5.5	V
Sense current pin (ISEN)	–0.3	2	V
Digital pin voltage range (SCLK, SCS, SMODE, SDATAI, SDATAO, FGOUT, FAULTn, LOCKn, CLKIN, BRAKE, DIR, ENABLE, RESET)	–0.5	5.75	V
Hall sensor input pin voltage (UHP, UHN, VHP, VHN, WHP, WHN, FGFB, FGINN/TACH, FGINP)	0	VREG	V
Continuous total power dissipation	See Thermal Information
Operating junction temperature range, T_J	–40	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground pin.

(3) Power dissipation and thermal limits must be observed

6.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–60	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	-4000	4000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	-1500	1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
V_M	Motor power supply voltage range, ENABLE = 1, motor operating⁽³⁾		8.5	32	V
V_MDIS	Motor power supply voltage range, ENABLE = 0, motor not operating		4.5	35	V
I_VREG	VREG output current⁽¹⁾		0	30	mA
I_VSW	VSW output current⁽¹⁾		0	30	mA
f_HALL	Hall sensor input frequency⁽⁴⁾		0	30	kHz
f_CLKIN	Frequency on CLKIN	SPDMODE = 00 (Clock Frequency Mode)	0	90
f_CLKIN	Frequency on CLKIN	SPDMODE = 01 (Clock PWM Mode)	16	50 ⁽²⁾

(1) Power dissipation and thermal limits must be observed

(2) Operational with frequencies above 50 kHz, but resolution is degraded

(3) Note that at VM < 12 V, gate drive output voltage tracks VM voltage

(4) f_HALL of 50 Hz to 6.7 kHz is best

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DRV8308	UNIT
		RHA (VQFN)
		40 PINS
R_θJA	Junction-to-ambient thermal resistance	33.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	23	°C/W
R_θJB	Junction-to-board thermal resistance	8.8	°C/W
ψ_JT	Junction-to-top characterization parameter	0.3	°C/W
ψ_JB	Junction-to-board characterization parameter	8.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VM SUPPLY
I_VM	VM active current	ENABLE = active, VREG and VSW open		12	18	mA
I_STBY	VM standby current	ENABLE = inactive			120	µA
V_RESET	VM logic reset voltage	VM falling			4.6	V
V_RESET	VM logic reset voltage	VM rising	5			V
VREG SUPPLY
V_VREG	Output voltage	I_OUT = 1 to 30 mA	4.75	5	5.25	V
I_VREG	Output current				30	mA
VSW SUPPLY
R_DS(ON)	VSW switch on-resistance	I_OUT = 1 to 30 mA		9	20	Ω
I_VSW	Output current				30	mA
INTERNAL CLOCK OSCILLATOR
f_CLK50	Internal CLK50 clock frequency			50		MHz
LOGIC-LEVEL INPUTS AND OUTPUTS
V_IL	Low-level input voltage				0.8	V
V_IH	High-level input voltage		1.5		5.5	V
I_IL	Low-level input current		–50		50	µA
I_IH	High-level input current	V_IN = 3.3 V, RESET, DIR, BRAKE, CLKIN, SCS, SCLK, SDATAI, SMODE	20		100	µA
I_IH	High-level input current	V_IN = 3.3 V, ENABLE	6		9	µA
V_HYS	Input hysteresis voltage		0.1	0.3	0.5	V
R_PD	Input pulldown resistance	RESET, DIR, BRAKE, CLKIN, SCS, SCLK, SDATAI, SMODE	50	100	150	kΩ
R_PD	Input pulldown resistance	ENABLE	350		550	kΩ
OPEN DRAIN OUTPUTS
V_OL	Low-level output voltage	I_OUT = 2.0 mA			0.5	V
I_OH	Output leakage current	V_OUT = 3.3 V			1	µA
FG AMPLIFIER AND COMPARATOR
V_IO	FG amplifier input offset voltage		–7		7	mV
I_IB	FG amplifier input bias current		–1		1	μA
V_ICM	FG amplifier input common mode voltage range		1.5		3.5	V
A_V	FG amplifier open loop voltage gain		45			dB
GBW	FG amplifier gain bandwidth product		500			kHz
V_REF+	FG comparator positive reference voltage		–20%	V_VREG / 2	20%	V
V_IT+	FG comparator positive threshold		–20%	V_VREG / 1.8	20%	V
V_IT-	FG comparator negative threshold		–20%	V_VREG / 2	20%	V
HALL SENSOR INPUTS
V_HYS	Hall amplifier hysteresis voltage		15	20	25	mV
?V_HYS	Hall amplifier hysteresis difference	Between U, V, W	–5		5	mV
V_ID	Hall amplifier input differential		50			mV
V_CM	Hall amplifier input common mode voltage range		1.5		3.5	V
I_IN	Input leakage current	H_x+ = H_x-	–10		10	μA
t_HDEG	Hall deglitch time			20		μs
MOSFET DRIVERS
V_OUTH	High-side gate drive output voltage	I_O = 100 μA, VM ≥ 12V		VM + 10		V
V_OUTL	Low-side gate drive output voltage	I_O = 100 μA		10		V
I_OUT	Peak gate drive current	IDRIVE = 000		10		mA
		IDRIVE = 001		20
		IDRIVE = 010		30
		IDRIVE = 011		50
		IDRIVE = 100		90
		IDRIVE = 101		100
		IDRIVE = 110		110
		IDRIVE = 111		130
CYCLE-BY-CYCLE CURRENT LIMITER
V_LIMITER	Voltage limit across R_ISENSE for the current limiter		0.225	0.25	0.275	V
t_BLANK	Time that V_LIMITER is ignored, from the start of the PWM cycle	OCPDEG = 00		2		µs
		OCPDEG = 01		3
		OCPDEG = 10		3.75
		OCPDEG = 11		6
PROTECTION CIRCUITS
V_SENSEOCP	Voltage limit across R_ISENSE for overcurrent protection		1.7	1.8	1.9	V
V_FETOCP	Voltage limit across each external FET’s drain to source for overcurrent protection	OCPTH = 00	200	250	400	mV
		OCPTH = 01	400	500	600
		OCPTH = 10	600	750	850
		OCPTH = 11	850	1000	1200
t_OCP	Deglitch time for V_SENSEOCP or V_FETOCP to trigger	OCPDEG = 00		1.6		µs
		OCPDEG = 01		2.3
		OCPDEG = 10		3
		OCPDEG = 11		5
V_UVLO	VM undervoltage lockout	VM rising		8		V
V_UVLO	VM undervoltage lockout	VM falling		7.8		V
V_OVLO	VM overvoltage lockout	VM rising, OVTH = 0	32	34.5	36	V
V_OVLO	VM overvoltage lockout	VM rising, OVTH = 1		28	29	V
t_RETRY	Fault retry time after OTS	RETRY = 1		5		s
T_TSD	Thermal shutdown die temperature		150	160		°C
V_CPFAIL	VCP failure threshold (CPFAIL bit)			VM + 3		V

6.6 SPI Timing Requirements

T_A = 25°C, over recommended operating conditions unless otherwise noted ⁽¹⁾

NUMBER⁽²⁾			MIN	MAX	UNIT
1	t_CYC	Clock cycle time	62		ns
2	t_CLKH	Clock high time	25
3	t_CLKL	Clock low time	25
4	t_SU(SDATI)	Setup time, SDATI to SCLK	5
5	t_H(SDATI)	Hold time, SDATI to SCLK	1
6	t_SU(SCS)	Setup time, SCS to SCLK	5
7	t_H(SCS)	Hold time, SCS to SCLK	1
8	t_L(SCS)	Inactive time, SCS (between writes)	100
9	t_D(SDATO)	Delay time, SCLK to SDATO (during read)		10
	t_AWAKE	Wake time (ENABLE active to high-side gate drive enabled)		1	ms
	t_SPI	Delay from power-up or RESET low until serial interface functional		10	μs

(1) SMODE = Low

(2) These numbers refer to the corresponding number in Figure 1

Figure 1. SPI Timing Requirements

6.7 Typical Characteristics

DRV8308 VSW_vs_current_with_VM_12V_slvscf7.png

Figure 2. VSW vs Current with VM = 12V

DRV8308 VREG_vs_current_with_VM_12V_slvscf7.png

Figure 3. VREG vs Current with VM = 12V