ZHCSC39B February 2014 – November 2017 DRV8308
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configurations and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Hall Comparators
- 7.3.2 FG Amplifier, Comparator, and FG Output
- 7.3.3 Enable, Reset, and Clock Generation
- 7.3.4 Commutation
- 7.3.5 Commutation Logic Block Diagram
- 7.3.6 Commutation Parameters
- 7.3.7 Braking
- 7.3.8 Output Pre-Drivers
- 7.3.9 Current Limit
- 7.3.10 Charge Pump
- 7.3.11 5-V Linear Regulator
- 7.3.12 Power Switch
- 7.3.13 Protection Circuits
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Map
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
5 Pin Configurations and Functions
RHA Package
40-Pin VQFN With Exposed Thermal Pad
Top View
Pin Functions
| PIN | I/O(1) | DESCRIPTION | EXTERNAL COMPONENTS OR CONNECTIONS | |
|---|---|---|---|---|
| NAME | NO. | |||
| POWER AND GROUND | ||||
| CP1 | 30 | PWR | Charge pump flying capacitor | Connect a 0.1-μF 35-V capacitor between CP1 and CP2 |
| CP2 | 29 | PWR | ||
| GND | 26, PPAD | PWR | Ground reference. Pin 26 and the exposed thermal pad are internally connected. | Connect to board GND |
| VCP | 28 | PWR | Charge pump storage capacitor | Connect a 1-μF 35-V ceramic capacitor to VM |
| VINT | 25 | PWR | Internal 1.8-V core voltage regulator bypass | Bypass to GND with a 1-μF 6.3-V ceramic capacitor |
| VM | 27 | PWR | Motor supply voltage | Connect to motor supply voltage. Bypass to GND with a 0.1-μF ceramic capacitor, plus a large electrolytic capacitor (47 μF or larger is recommended), with a voltage rating of 1.5× to 2.5× VM. |
| VREG | 24 | PWR | 5-V regulator output. Active when ENABLE is active. | Bypass to GND with a 0.1-μF 10-V ceramic capacitor. Can provide 5-V power to Hall sensors. |
| VSW | 7 | PWR | Switched VM power output. When ENABLE is active, VM is applied to this pin. | Can be used for powering Hall elements, along with added series resistance. |
| CONTROL | ||||
| BRAKE | 20 | I | Causes motor to brake. Polarity is programmable. Internal pulldown resistor. | |
| CLKIN | 19 | I | The clock input, used in Clock Frequency Mode and Clock PWM Mode. Internal pulldown resistor. | |
| DIR | 21 | I | Sets motor rotation direction. Polarity is programmable. Internal pulldown resistor. | |
| ENABLE | 22 | I | Enables and disables motor. Polarity is programmable. Internal pulldown resistor. | |
| FAULTn | 17 | OD | Fault indicator – active low when overcurrent, or overtemperature. Open-drain output. | |
| FGOUT | 16 | OD | Outputs a TACH signal generated from the FG amplifier or Hall sensors. Open-drain output. | |
| LOCKn | 18 | OD | Outputs a signal that indicates the speed loop is locked. Open-drain output. | |
| RESET | 23 | I | Active high to reset all internal logic. Internal pulldown resistor. | |
| SERIAL INTERFACE | ||||
| SCLK(2) | 11 | I/OD | Serial clock | SPI mode: Serial clock input. Data is clocked on rising edges. Internal pulldown resistor. EEPROM mode: Connect to EEPROM CLK. Open-drain output requires external pullup. |
| SCS(2) | 12 | I/OD | Serial chip select | SPI mode: Active high enables serial interface operation. Internal pulldown resistor. EEPROM mode: Connect to EEPROM CS. Open-drain output requires external pullup. |
| SDATAI | 14 | I | Serial data input | SPI mode: Serial data input. Internal pulldown resistor. EEPROM mode: Serial data input. Connect to EEPROM DO terminal. |
| SDATAO | 15 | OD | Serial data output | SPI mode: Serial data output. Open-drain output. EEPROM mode: Connect to EEPROM DI. Open-drain output requires external pullup. |
| SMODE | 13 | I | Serial mode | SPI mode: leave open or connect to ground for SPI interface mode. EEPROM mode: Connect to logic high to for EEPROM mode. |
| POWER STAGE INTERFACE | ||||
| ISEN | 31 | I | Low-side current sense resistor | Connect to low-side current sense resistor |
| U | 33 | I | Measures motor phase voltages for VFETOCP | Connect to motor windings |
| V | 36 | I | ||
| W | 39 | I | ||
| UHSG | 32 | O | High-side FET gate outputs | Connect to high-side 1/2-H N-channel FET gate |
| VHSG | 35 | O | ||
| WHSG | 38 | O | ||
| ULSG | 34 | O | Low-side FET gate outputs | Connect to low-side 1/2-H N-channel FET gate |
| VLSG | 37 | O | ||
| WLSG | 40 | O | ||
| HALL AND FG INTERFACE | ||||
| FGFB | 8 | O | FG amplifier feedback pin | Connect feedback network to FGIN– |
| FGINN_TACH | 9 | I(3) | FG amplifier negative input or TACH input | Connect to FG trace and filter components. When using a TACH with FGSEL= 3, connect a logic-level TACH signal. If unused, connect FGFB to FG–. |
| FGINP | 10 | I/O | FG amplifier positive input | Connect to FG trace and filter components on the PCB (if used). |
| UHP | 1 | I | Hall sensor U positive input | Connect to Hall sensors. Noise filter capacitors may be desirable, connected between the + and – Hall inputs. |
| UHN | 2 | I | Hall sensor U negative input | |
| VHP | 3 | I | Hall sensor V positive input | |
| VHN | 4 | I | Hall sensor V negative input | |
| WHP | 5 | I | Hall sensor W positive input | |
| WHN | 6 | I | Hall sensor W negative input | |
(1) I = input, O = output, OD = open-drain output, I/O = input/output
(2) In SPI mode, these pins are inputs; in EEPROM mode, they are open-drain outputs.
(3) When using FG amplifier, this pin is an analog input. If in TACH mode, this is a logic-level input.